ADC CM11

Collaboration diagram for ADC CM11:

Data Structures
struct	CHAN_SETTINGS_T
union	tr_sadc_ana_set1_s
struct	ADC_REGISTERS_T
	the struct we use so we can address registers using field names More...
struct	tr_hal_adc_settings_t

Macros
#define	TR_HAL_NUM_ADC   4
#define	MAX_ADC_CHANNEL_ID   ADC_CHANNEL_3_ID
#define	TR_HAL_ADC_CHANNEL_NONE   0xFF
#define	TR_HAL_ADC_AIO4   28
#define	TR_HAL_ADC_AIO5   29
#define	TR_HAL_ADC_AIO6   30
#define	TR_HAL_ADC_AIO7   31
#define	ADC_VALID_PIN_CHOICE1   TR_HAL_ADC_AIO4
#define	ADC_VALID_PIN_CHOICE2   TR_HAL_ADC_AIO5
#define	ADC_VALID_PIN_CHOICE3   TR_HAL_ADC_AIO6
#define	ADC_VALID_PIN_CHOICE4   TR_HAL_ADC_AIO7
#define	DEFAULT_ADC_PIN   TR_HAL_ADC_AIO4
#define	TR_ADC_ENABLE_AIO4   0x10UL
#define	TR_ADC_ENABLE_AIO5   0x20UL
#define	TR_ADC_ENABLE_AIO6   0x40UL
#define	TR_ADC_ENABLE_AIO7   0x80UL
#define	CHIP_MEMORY_MAP_ADC_BASE   (0xA0D00000UL)
	chip register addresses section 3.1 of the data sheet explains the Memory map. this gives the base address for how to write the chip registers the chip registers are how the software interacts and configures the HAL peripherals. We create a struct below that addresses the individual registers. This makes it so we can use this base address and a struct field to read or write a chip register
#define	analog_settings0   ch_x_setting[9].ch_x_reserved
#define	ADC_REG_ENABLE_ADC_DISABLE   0x000
#define	ADC_REG_ENABLE_ADC_ENABLE   0x001
#define	ADC_REG_ENABLE_FREE_RUN_CLOCK   0x100
#define	ADC_REG_ENABLE_FREE_RUN_ENGINE   0x200
#define	ADC_REG_RESET_ADC   0x001
#define	ADC_REG_RESET_FIFO   0x100
#define	ADC_REG_START_ADC   0x01
#define	ADC_REG_TIMER_RATE_DEPENDS_ON_SOFTWARE   0x00
#define	ADC_REG_TIMER_RATE_DEPENDS_ON_TIMER   0x01
#define	ADC_REG_TIMER_USE_SYSTEM_CLOCK   0x00
#define	ADC_REG_TIMER_USE_SLOW_CLOCK   0x02
#define	ADC_REG_TIMER_RISING_EDGE   0x00
#define	ADC_REG_TIMER_FALLING_EDGE   0x04
#define	ADC_REG_TIMER_DEBUG_MASK   0x78
#define	ADC_REG_TIMER_CLOCK_DIV_MASK   0xFFFF0000
#define	ADC_REG_TIMER_CLOCK_DIV_SHIFT   16
#define	TR_HAL_ADC_MAX_CLOCK_DIVISOR   65536
#define	TR_HAL_ADC_MIN_CLOCK_DIVISOR   3
#define	ADC_REG_SAMPLE_OUTPUT_RESOLUTION_8_BIT   0x00
#define	ADC_REG_SAMPLE_OUTPUT_RESOLUTION_10_BIT   0x01
#define	ADC_REG_SAMPLE_OUTPUT_RESOLUTION_12_BIT   0x02
#define	ADC_REG_SAMPLE_OUTPUT_RESOLUTION_14_BIT   0x03
#define	ADC_REG_SAMPLE_SELECT_CHANNEL_0   0x00
#define	ADC_REG_SAMPLE_SELECT_CHANNEL_1   0x10
#define	ADC_REG_SAMPLE_SELECT_CHANNEL_2   0x20
#define	ADC_REG_SAMPLE_SELECT_CHANNEL_3   0x30
#define	ADC_REG_SAMPLE_SELECT_CHANNEL_4   0x40
#define	ADC_REG_SAMPLE_SELECT_CHANNEL_5   0x50
#define	ADC_REG_SAMPLE_SELECT_CHANNEL_6   0x60
#define	ADC_REG_SAMPLE_SELECT_CHANNEL_7   0x70
#define	ADC_REG_SAMPLE_SELECT_CHANNEL_8   0x80
#define	ADC_REG_SAMPLE_SELECT_CHANNEL_9   0x90
#define	ADC_REG_SAMPLE_VALUE_BYPASS   0x1000
#define	ADC_REG_SAMPLE_MSB_BIT_INVERSION   0x2000
#define	ADC_REG_SAMPLE_ENABLE_MANUAL_MODE1   0x4000
#define	ADC_REG_SAMPLE_ENABLE_MANUAL_MODE2   0x8000
#define	ADC_REG_SAMPLE_CALIBRATION_MASK   0x0FFF0000
#define	ADC_CONFIG_REG_P_CHANNEL_AIN_0   0x00000000
#define	ADC_CONFIG_REG_P_CHANNEL_AIN_1   0x00000001
#define	ADC_CONFIG_REG_P_CHANNEL_AIN_2   0x00000002
#define	ADC_CONFIG_REG_P_CHANNEL_AIN_3   0x00000003
#define	ADC_CONFIG_REG_P_CHANNEL_AIN_4   0x00000004
#define	ADC_CONFIG_REG_P_CHANNEL_AIN_5   0x00000005
#define	ADC_CONFIG_REG_P_CHANNEL_AIN_6   0x00000006
#define	ADC_CONFIG_REG_P_CHANNEL_AIN_7   0x00000007
#define	ADC_CONFIG_REG_P_CHANNEL_NONE   0x0000000B
#define	ADC_CONFIG_REG_N_CHANNEL_AIN_0   0x00000000
#define	ADC_CONFIG_REG_N_CHANNEL_AIN_1   0x00000010
#define	ADC_CONFIG_REG_N_CHANNEL_AIN_2   0x00000020
#define	ADC_CONFIG_REG_N_CHANNEL_AIN_3   0x00000030
#define	ADC_CONFIG_REG_N_CHANNEL_AIN_4   0x00000040
#define	ADC_CONFIG_REG_N_CHANNEL_AIN_5   0x00000050
#define	ADC_CONFIG_REG_N_CHANNEL_AIN_6   0x00000060
#define	ADC_CONFIG_REG_N_CHANNEL_AIN_7   0x00000070
#define	ADC_CONFIG_REG_N_CHANNEL_NONE   0x000000B0
#define	ADC_CONFIG_REG_MAX_GAIN_SETTING   63
#define	ADC_CONFIG_REG_DEFAULT_GAIN   0x00001400
#define	ADC_CONFIG_REG_SELECT_REF_IN   0x00004000
#define	ADC_CONFIG_REG_P_CHAN_PULL_NONE   0x00000000
#define	ADC_CONFIG_REG_P_CHAN_PULL_HIGH   0x00010000
#define	ADC_CONFIG_REG_P_CHAN_PULL_LOW   0x00020000
#define	ADC_CONFIG_REG_P_CHAN_VCM_VOLTAGE   0x00030000
#define	ADC_CONFIG_REG_N_CHAN_PULL_NONE   0x00000000
#define	ADC_CONFIG_REG_N_CHAN_PULL_HIGH   0x00040000
#define	ADC_CONFIG_REG_N_CHAN_PULL_LOW   0x00080000
#define	ADC_CONFIG_REG_N_CHAN_VCM_VOLTAGE   0x000C0000
#define	ADC_CONFIG_REG_PULL_NONE   0x00000000
#define	ADC_CONFIG_REG_PULL_VCM_MODE   0x000F0000
#define	ADC_CONFIG_REG_AQUISITION_TIME_0p3_uS   0x00000000
#define	ADC_CONFIG_REG_AQUISITION_TIME_1_uS   0x01000000
#define	ADC_CONFIG_REG_AQUISITION_TIME_2_uS   0x02000000
#define	ADC_CONFIG_REG_AQUISITION_TIME_3_uS   0x03000000
#define	ADC_CONFIG_REG_AQUISITION_TIME_4_uS   0x04000000
#define	ADC_CONFIG_REG_AQUISITION_TIME_8_uS   0x05000000
#define	ADC_CONFIG_REG_AQUISITION_TIME_12_uS   0x06000000
#define	ADC_CONFIG_REG_AQUISITION_TIME_16_uS   0x07000000
#define	ADC_CONFIG_REG_END_DELAY_TIME_0p3_uS   0x00000000
#define	ADC_CONFIG_REG_END_DELAY_TIME_1_uS   0x10000000
#define	ADC_CONFIG_REG_END_DELAY_TIME_2_uS   0x20000000
#define	ADC_CONFIG_REG_END_DELAY_TIME_3_uS   0x30000000
#define	ADC_CONFIG_REG_END_DELAY_TIME_4_uS   0x40000000
#define	ADC_CONFIG_REG_END_DELAY_TIME_8_uS   0x50000000
#define	ADC_CONFIG_REG_END_DELAY_TIME_12_uS   0x60000000
#define	ADC_CONFIG_REG_END_DELAY_TIME_16_uS   0x70000000
#define	ADC_CONFIG_REG_CLEAR_VALUE   0x240000FF
#define	ADC_BURST_REG_DISABLE_BURST   0x00
#define	ADC_BURST_REG_ENABLE_BURST   0x01
#define	ADC_THRESHHOLD_LOW_DEFAULT   0x00000000
#define	ADC_THRESHHOLD_HIGH_DEFAULT   0x3FFF0000
#define	ADC_ENDMA_REG_ENABLE_DMA   0x01
#define	ADC_ENDMA_REG_RESET_DMA   0x01
#define	TR_HAL_ADC_INTERRUPT_DMA   0x000001
#define	TR_HAL_ADC_INTERRUPT_DONE   0x000004
#define	TR_HAL_ADC_INTERRUPT_VALID   0x000008
#define	TR_HAL_ADC_INTERRUPT_MODE_DONE   0x000010
#define	TR_HAL_ADC_INTERRUPT_CHAN_0   0x040000
#define	TR_HAL_ADC_INTERRUPT_CHAN_1   0x080000
#define	TR_HAL_ADC_INTERRUPT_CHAN_2   0x100000
#define	TR_HAL_ADC_INTERRUPT_CHAN_3   0x200000
#define	TR_HAL_ADC_INTERRUPT_LOW_THRESH   0x0003FF00
#define	TR_HAL_ADC_INTERRUPT_HIGH_THRESH   0x0FFC0000
#define	TR_HAL_ADC_INTERRUPT_ALL   0x0FFFFF1D
#define	TR_HAL_ADC_INTERRUPT_BASE   0x0000001D
#define	TR_HAL_ADC_EVENT_CH_0_RESULT   0x01
#define	TR_HAL_ADC_EVENT_CH_1_RESULT   0x02
#define	TR_HAL_ADC_EVENT_CH_2_RESULT   0x04
#define	TR_HAL_ADC_EVENT_CH_3_RESULT   0x08
#define	TR_HAL_ADC_EVENT_ALL_CH_DONE   0x10
#define	TR_HAL_ADC_EVENT_DMA   0x20
#define	TR_HAL_ADC_R0_RESULT_MASK   0x00003FFF
#define	TR_HAL_ADC_R1_RESULT_MASK   0x00000FFF
#define	TR_HAL_ADC_R2_RESULT_MASK   0x00000FFF
#define	ADC_REGISTERS   ((ADC_REGISTERS_T *) CHIP_MEMORY_MAP_ADC_BASE)
#define	TR_HAL_ADC_DEFAULT_GAIN   18
#define	TR_HAL_ADC_THRESH_LOW_DEFAULT   0x0000
#define	TR_HAL_ADC_THRESH_HIGH_DEFAULT   0x3FFF
#define	DEFAULT_ADC_SINGLE_ENDED_CONFIG

Typedefs
typedef union tr_sadc_ana_set1_s	tr_sadc_ana_set1_t
typedef void(*	tr_hal_adc_event_callback_t) (uint32_t raw_result, uint32_t converted_result, uint32_t event_bitmask, uint32_t int_status)

Enumerations
enum	tr_hal_adc_channel_id_t {   ADC_CHANNEL_0_ID = 0 ,   ADC_CHANNEL_1_ID = 1 ,   ADC_CHANNEL_2_ID = 2 ,   ADC_CHANNEL_3_ID = 3 }
enum	tr_hal_adc_oversample_t {   TR_HAL_ADC_REG_SAMPLE_NO_OVERSAMPLE = 0x000 ,   TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_2 = 0x100 ,   TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_4 = 0x200 ,   TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_8 = 0x300 ,   TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_16 = 0x400 ,   TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_32 = 0x500 ,   TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_64 = 0x600 ,   TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_128 = 0x700 ,   TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_256 = 0x800 }
enum	tr_hal_adc_mode_t {   TR_HAL_ADC_MODE_ONE_SHOT = 0 ,   TR_HAL_ADC_MODE_TIMER = 1 ,   TR_HAL_ADC_MODE_SCAN = 2 }
enum	tr_hal_adc_resolution_t {   TR_HAL_ADC_MODE_RESOLUTION_8_BIT = ADC_REG_SAMPLE_OUTPUT_RESOLUTION_8_BIT ,   TR_HAL_ADC_MODE_RESOLUTION_10_BIT = ADC_REG_SAMPLE_OUTPUT_RESOLUTION_10_BIT ,   TR_HAL_ADC_MODE_RESOLUTION_12_BIT = ADC_REG_SAMPLE_OUTPUT_RESOLUTION_12_BIT ,   TR_HAL_ADC_MODE_RESOLUTION_14_BIT = ADC_REG_SAMPLE_OUTPUT_RESOLUTION_14_BIT }
enum	tr_hal_adc_pull_mode_t {   TR_HAL_ADC_PULL_LOW = 0 ,   TR_HAL_ADC_PULL_HIGH = 1 ,   TR_HAL_ADC_PULL_SINGLE_ENDED = 2 ,   TR_HAL_ADC_PULL_NOT_USED = 3 }
enum	tr_hal_adc_clock_t {   TR_HAL_ADC_USE_SYSTEM_CLOCK = 0 ,   TR_HAL_ADC_USE_SLOW_CLOCK = 1 }
enum	tr_hal_time_t {   TR_HAL_ADC_TIME_HALF = 0 ,   TR_HAL_ADC_TIME_1 = 1 ,   TR_HAL_ADC_TIME_2 = 2 ,   TR_HAL_ADC_TIME_3 = 3 ,   TR_HAL_ADC_TIME_4 = 4 ,   TR_HAL_ADC_TIME_8 = 5 ,   TR_HAL_ADC_TIME_12 = 6 ,   TR_HAL_ADC_TIME_16 = 7 }

Detailed Description

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Macro Definition Documentation

ADC_BURST_REG_DISABLE_BURST

#define ADC_BURST_REG_DISABLE_BURST   0x00

ADC_BURST_REG_ENABLE_BURST

#define ADC_BURST_REG_ENABLE_BURST   0x01

ADC_CONFIG_REG_AQUISITION_TIME_0p3_uS

#define ADC_CONFIG_REG_AQUISITION_TIME_0p3_uS   0x00000000

ADC_CONFIG_REG_AQUISITION_TIME_12_uS

#define ADC_CONFIG_REG_AQUISITION_TIME_12_uS   0x06000000

ADC_CONFIG_REG_AQUISITION_TIME_16_uS

#define ADC_CONFIG_REG_AQUISITION_TIME_16_uS   0x07000000

ADC_CONFIG_REG_AQUISITION_TIME_1_uS

#define ADC_CONFIG_REG_AQUISITION_TIME_1_uS   0x01000000

ADC_CONFIG_REG_AQUISITION_TIME_2_uS

#define ADC_CONFIG_REG_AQUISITION_TIME_2_uS   0x02000000

ADC_CONFIG_REG_AQUISITION_TIME_3_uS

#define ADC_CONFIG_REG_AQUISITION_TIME_3_uS   0x03000000

ADC_CONFIG_REG_AQUISITION_TIME_4_uS

#define ADC_CONFIG_REG_AQUISITION_TIME_4_uS   0x04000000

ADC_CONFIG_REG_AQUISITION_TIME_8_uS

#define ADC_CONFIG_REG_AQUISITION_TIME_8_uS   0x05000000

ADC_CONFIG_REG_CLEAR_VALUE

#define ADC_CONFIG_REG_CLEAR_VALUE   0x240000FF

ADC_CONFIG_REG_DEFAULT_GAIN

#define ADC_CONFIG_REG_DEFAULT_GAIN   0x00001400

ADC_CONFIG_REG_END_DELAY_TIME_0p3_uS

#define ADC_CONFIG_REG_END_DELAY_TIME_0p3_uS   0x00000000

ADC_CONFIG_REG_END_DELAY_TIME_12_uS

#define ADC_CONFIG_REG_END_DELAY_TIME_12_uS   0x60000000

ADC_CONFIG_REG_END_DELAY_TIME_16_uS

#define ADC_CONFIG_REG_END_DELAY_TIME_16_uS   0x70000000

ADC_CONFIG_REG_END_DELAY_TIME_1_uS

#define ADC_CONFIG_REG_END_DELAY_TIME_1_uS   0x10000000

ADC_CONFIG_REG_END_DELAY_TIME_2_uS

#define ADC_CONFIG_REG_END_DELAY_TIME_2_uS   0x20000000

ADC_CONFIG_REG_END_DELAY_TIME_3_uS

#define ADC_CONFIG_REG_END_DELAY_TIME_3_uS   0x30000000

ADC_CONFIG_REG_END_DELAY_TIME_4_uS

#define ADC_CONFIG_REG_END_DELAY_TIME_4_uS   0x40000000

ADC_CONFIG_REG_END_DELAY_TIME_8_uS

#define ADC_CONFIG_REG_END_DELAY_TIME_8_uS   0x50000000

ADC_CONFIG_REG_MAX_GAIN_SETTING

#define ADC_CONFIG_REG_MAX_GAIN_SETTING   63

ADC_CONFIG_REG_N_CHAN_PULL_HIGH

#define ADC_CONFIG_REG_N_CHAN_PULL_HIGH   0x00040000

ADC_CONFIG_REG_N_CHAN_PULL_LOW

#define ADC_CONFIG_REG_N_CHAN_PULL_LOW   0x00080000

ADC_CONFIG_REG_N_CHAN_PULL_NONE

#define ADC_CONFIG_REG_N_CHAN_PULL_NONE   0x00000000

ADC_CONFIG_REG_N_CHAN_VCM_VOLTAGE

#define ADC_CONFIG_REG_N_CHAN_VCM_VOLTAGE   0x000C0000

ADC_CONFIG_REG_N_CHANNEL_AIN_0

#define ADC_CONFIG_REG_N_CHANNEL_AIN_0   0x00000000

ADC_CONFIG_REG_N_CHANNEL_AIN_1

#define ADC_CONFIG_REG_N_CHANNEL_AIN_1   0x00000010

ADC_CONFIG_REG_N_CHANNEL_AIN_2

#define ADC_CONFIG_REG_N_CHANNEL_AIN_2   0x00000020

ADC_CONFIG_REG_N_CHANNEL_AIN_3

#define ADC_CONFIG_REG_N_CHANNEL_AIN_3   0x00000030

ADC_CONFIG_REG_N_CHANNEL_AIN_4

#define ADC_CONFIG_REG_N_CHANNEL_AIN_4   0x00000040

ADC_CONFIG_REG_N_CHANNEL_AIN_5

#define ADC_CONFIG_REG_N_CHANNEL_AIN_5   0x00000050

ADC_CONFIG_REG_N_CHANNEL_AIN_6

#define ADC_CONFIG_REG_N_CHANNEL_AIN_6   0x00000060

ADC_CONFIG_REG_N_CHANNEL_AIN_7

#define ADC_CONFIG_REG_N_CHANNEL_AIN_7   0x00000070

ADC_CONFIG_REG_N_CHANNEL_NONE

#define ADC_CONFIG_REG_N_CHANNEL_NONE   0x000000B0

ADC_CONFIG_REG_P_CHAN_PULL_HIGH

#define ADC_CONFIG_REG_P_CHAN_PULL_HIGH   0x00010000

ADC_CONFIG_REG_P_CHAN_PULL_LOW

#define ADC_CONFIG_REG_P_CHAN_PULL_LOW   0x00020000

ADC_CONFIG_REG_P_CHAN_PULL_NONE

#define ADC_CONFIG_REG_P_CHAN_PULL_NONE   0x00000000

ADC_CONFIG_REG_P_CHAN_VCM_VOLTAGE

#define ADC_CONFIG_REG_P_CHAN_VCM_VOLTAGE   0x00030000

ADC_CONFIG_REG_P_CHANNEL_AIN_0

#define ADC_CONFIG_REG_P_CHANNEL_AIN_0   0x00000000

ADC_CONFIG_REG_P_CHANNEL_AIN_1

#define ADC_CONFIG_REG_P_CHANNEL_AIN_1   0x00000001

ADC_CONFIG_REG_P_CHANNEL_AIN_2

#define ADC_CONFIG_REG_P_CHANNEL_AIN_2   0x00000002

ADC_CONFIG_REG_P_CHANNEL_AIN_3

#define ADC_CONFIG_REG_P_CHANNEL_AIN_3   0x00000003

ADC_CONFIG_REG_P_CHANNEL_AIN_4

#define ADC_CONFIG_REG_P_CHANNEL_AIN_4   0x00000004

ADC_CONFIG_REG_P_CHANNEL_AIN_5

#define ADC_CONFIG_REG_P_CHANNEL_AIN_5   0x00000005

ADC_CONFIG_REG_P_CHANNEL_AIN_6

#define ADC_CONFIG_REG_P_CHANNEL_AIN_6   0x00000006

ADC_CONFIG_REG_P_CHANNEL_AIN_7

#define ADC_CONFIG_REG_P_CHANNEL_AIN_7   0x00000007

ADC_CONFIG_REG_P_CHANNEL_NONE

#define ADC_CONFIG_REG_P_CHANNEL_NONE   0x0000000B

ADC_CONFIG_REG_PULL_NONE

#define ADC_CONFIG_REG_PULL_NONE   0x00000000

ADC_CONFIG_REG_PULL_VCM_MODE

#define ADC_CONFIG_REG_PULL_VCM_MODE   0x000F0000

ADC_CONFIG_REG_SELECT_REF_IN

#define ADC_CONFIG_REG_SELECT_REF_IN   0x00004000

ADC_ENDMA_REG_ENABLE_DMA

#define ADC_ENDMA_REG_ENABLE_DMA   0x01

ADC_ENDMA_REG_RESET_DMA

#define ADC_ENDMA_REG_RESET_DMA   0x01

ADC_REG_ENABLE_ADC_DISABLE

#define ADC_REG_ENABLE_ADC_DISABLE   0x000

ADC_REG_ENABLE_ADC_ENABLE

#define ADC_REG_ENABLE_ADC_ENABLE   0x001

ADC_REG_ENABLE_FREE_RUN_CLOCK

#define ADC_REG_ENABLE_FREE_RUN_CLOCK   0x100

ADC_REG_ENABLE_FREE_RUN_ENGINE

#define ADC_REG_ENABLE_FREE_RUN_ENGINE   0x200

ADC_REG_RESET_ADC

#define ADC_REG_RESET_ADC   0x001

ADC_REG_RESET_FIFO

#define ADC_REG_RESET_FIFO   0x100

ADC_REG_SAMPLE_CALIBRATION_MASK

#define ADC_REG_SAMPLE_CALIBRATION_MASK   0x0FFF0000

ADC_REG_SAMPLE_ENABLE_MANUAL_MODE1

#define ADC_REG_SAMPLE_ENABLE_MANUAL_MODE1   0x4000

ADC_REG_SAMPLE_ENABLE_MANUAL_MODE2

#define ADC_REG_SAMPLE_ENABLE_MANUAL_MODE2   0x8000

ADC_REG_SAMPLE_MSB_BIT_INVERSION

#define ADC_REG_SAMPLE_MSB_BIT_INVERSION   0x2000

ADC_REG_SAMPLE_OUTPUT_RESOLUTION_10_BIT

#define ADC_REG_SAMPLE_OUTPUT_RESOLUTION_10_BIT   0x01

ADC_REG_SAMPLE_OUTPUT_RESOLUTION_12_BIT

#define ADC_REG_SAMPLE_OUTPUT_RESOLUTION_12_BIT   0x02

ADC_REG_SAMPLE_OUTPUT_RESOLUTION_14_BIT

#define ADC_REG_SAMPLE_OUTPUT_RESOLUTION_14_BIT   0x03

ADC_REG_SAMPLE_OUTPUT_RESOLUTION_8_BIT

#define ADC_REG_SAMPLE_OUTPUT_RESOLUTION_8_BIT   0x00

ADC_REG_SAMPLE_SELECT_CHANNEL_0

#define ADC_REG_SAMPLE_SELECT_CHANNEL_0   0x00

ADC_REG_SAMPLE_SELECT_CHANNEL_1

#define ADC_REG_SAMPLE_SELECT_CHANNEL_1   0x10

ADC_REG_SAMPLE_SELECT_CHANNEL_2

#define ADC_REG_SAMPLE_SELECT_CHANNEL_2   0x20

ADC_REG_SAMPLE_SELECT_CHANNEL_3

#define ADC_REG_SAMPLE_SELECT_CHANNEL_3   0x30

ADC_REG_SAMPLE_SELECT_CHANNEL_4

#define ADC_REG_SAMPLE_SELECT_CHANNEL_4   0x40

ADC_REG_SAMPLE_SELECT_CHANNEL_5

#define ADC_REG_SAMPLE_SELECT_CHANNEL_5   0x50

ADC_REG_SAMPLE_SELECT_CHANNEL_6

#define ADC_REG_SAMPLE_SELECT_CHANNEL_6   0x60

ADC_REG_SAMPLE_SELECT_CHANNEL_7

#define ADC_REG_SAMPLE_SELECT_CHANNEL_7   0x70

ADC_REG_SAMPLE_SELECT_CHANNEL_8

#define ADC_REG_SAMPLE_SELECT_CHANNEL_8   0x80

ADC_REG_SAMPLE_SELECT_CHANNEL_9

#define ADC_REG_SAMPLE_SELECT_CHANNEL_9   0x90

ADC_REG_SAMPLE_VALUE_BYPASS

#define ADC_REG_SAMPLE_VALUE_BYPASS   0x1000

ADC_REG_START_ADC

#define ADC_REG_START_ADC   0x01

ADC_REG_TIMER_CLOCK_DIV_MASK

#define ADC_REG_TIMER_CLOCK_DIV_MASK   0xFFFF0000

ADC_REG_TIMER_CLOCK_DIV_SHIFT

#define ADC_REG_TIMER_CLOCK_DIV_SHIFT   16

ADC_REG_TIMER_DEBUG_MASK

#define ADC_REG_TIMER_DEBUG_MASK   0x78

ADC_REG_TIMER_FALLING_EDGE

#define ADC_REG_TIMER_FALLING_EDGE   0x04

ADC_REG_TIMER_RATE_DEPENDS_ON_SOFTWARE

#define ADC_REG_TIMER_RATE_DEPENDS_ON_SOFTWARE   0x00

ADC_REG_TIMER_RATE_DEPENDS_ON_TIMER

#define ADC_REG_TIMER_RATE_DEPENDS_ON_TIMER   0x01

ADC_REG_TIMER_RISING_EDGE

#define ADC_REG_TIMER_RISING_EDGE   0x00

ADC_REG_TIMER_USE_SLOW_CLOCK

#define ADC_REG_TIMER_USE_SLOW_CLOCK   0x02

ADC_REG_TIMER_USE_SYSTEM_CLOCK

#define ADC_REG_TIMER_USE_SYSTEM_CLOCK   0x00

ADC_REGISTERS

#define ADC_REGISTERS   ((ADC_REGISTERS_T *) CHIP_MEMORY_MAP_ADC_BASE)

ADC_THRESHHOLD_HIGH_DEFAULT

#define ADC_THRESHHOLD_HIGH_DEFAULT   0x3FFF0000

ADC_THRESHHOLD_LOW_DEFAULT

#define ADC_THRESHHOLD_LOW_DEFAULT   0x00000000

ADC_VALID_PIN_CHOICE1

#define ADC_VALID_PIN_CHOICE1   TR_HAL_ADC_AIO4

ADC_VALID_PIN_CHOICE2

#define ADC_VALID_PIN_CHOICE2   TR_HAL_ADC_AIO5

ADC_VALID_PIN_CHOICE3

#define ADC_VALID_PIN_CHOICE3   TR_HAL_ADC_AIO6

ADC_VALID_PIN_CHOICE4

#define ADC_VALID_PIN_CHOICE4   TR_HAL_ADC_AIO7

analog_settings0

#define analog_settings0   ch_x_setting[9].ch_x_reserved

CHIP_MEMORY_MAP_ADC_BASE

#define CHIP_MEMORY_MAP_ADC_BASE   (0xA0D00000UL)

chip register addresses section 3.1 of the data sheet explains the Memory map. this gives the base address for how to write the chip registers the chip registers are how the software interacts and configures the HAL peripherals. We create a struct below that addresses the individual registers. This makes it so we can use this base address and a struct field to read or write a chip register

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DEFAULT_ADC_PIN

#define DEFAULT_ADC_PIN   TR_HAL_ADC_AIO4

DEFAULT_ADC_SINGLE_ENDED_CONFIG

#define DEFAULT_ADC_SINGLE_ENDED_CONFIG

Value:

    {                                                            \
        .adc_pin_p = (tr_hal_gpio_pin_t) { DEFAULT_ADC_PIN },    \
        .adc_pin_n = (tr_hal_gpio_pin_t) { TR_HAL_PIN_NOT_SET }, \
        .mode = TR_HAL_ADC_MODE_ONE_SHOT,                        \
        .start_now = false,                                      \
        .resolution = TR_HAL_ADC_MODE_RESOLUTION_12_BIT,         \
        .vga_gain_in_dB = TR_HAL_ADC_DEFAULT_GAIN ,              \
        .pin_p_pull_mode = TR_HAL_ADC_PULL_SINGLE_ENDED,         \
        .pin_n_pull_mode = TR_HAL_ADC_PULL_NOT_USED,             \
        .aquisition_time = TR_HAL_ADC_TIME_16,                   \
        .end_delay_time = TR_HAL_ADC_TIME_16,                    \
        .clock_to_use = TR_HAL_ADC_USE_SLOW_CLOCK,               \
        .clock_divider = 4,                                      \
        .enable_burst_mode = false,                              \
        .oversample = TR_HAL_ADC_REG_SAMPLE_NO_OVERSAMPLE,       \
        .threshhold_low = TR_HAL_ADC_THRESH_LOW_DEFAULT,         \
        .threshhold_high = TR_HAL_ADC_THRESH_HIGH_DEFAULT,       \
        .interrupt_enabled = false,                              \
        .interrupt_priority = TR_HAL_INTERRUPT_PRIORITY_5,       \
        .event_handler_fx = NULL,                                \
        .enable_microvolt_conversion = true,                     \
        .min_expected_adc_reading = 3900,                        \
        .max_expected_adc_reading = 12500,                       \
        .min_microvolt_value = 0,                                \
        .max_microvolt_value = 3300000,                          \
    }

---

default values for a single ended (one pin) ADC that fires once and then when start API is called. Will call the event_handler_fx when the result is ready

---

MAX_ADC_CHANNEL_ID

#define MAX_ADC_CHANNEL_ID   ADC_CHANNEL_3_ID

TR_ADC_ENABLE_AIO4

#define TR_ADC_ENABLE_AIO4   0x10UL

TR_ADC_ENABLE_AIO5

#define TR_ADC_ENABLE_AIO5   0x20UL

TR_ADC_ENABLE_AIO6

#define TR_ADC_ENABLE_AIO6   0x40UL

TR_ADC_ENABLE_AIO7

#define TR_ADC_ENABLE_AIO7   0x80UL

TR_HAL_ADC_AIO4

#define TR_HAL_ADC_AIO4   28

---

valid pins for ADC we use pin 28 as the default this is the first of 4 pins that are available (28, 29, 30, 31)

---

TR_HAL_ADC_AIO5

#define TR_HAL_ADC_AIO5   29

TR_HAL_ADC_AIO6

#define TR_HAL_ADC_AIO6   30

TR_HAL_ADC_AIO7

#define TR_HAL_ADC_AIO7   31

TR_HAL_ADC_CHANNEL_NONE

#define TR_HAL_ADC_CHANNEL_NONE   0xFF

TR_HAL_ADC_DEFAULT_GAIN

#define TR_HAL_ADC_DEFAULT_GAIN   18

---

ADC gain

---

TR_HAL_ADC_EVENT_ALL_CH_DONE

#define TR_HAL_ADC_EVENT_ALL_CH_DONE   0x10

TR_HAL_ADC_EVENT_CH_0_RESULT

#define TR_HAL_ADC_EVENT_CH_0_RESULT   0x01

TR_HAL_ADC_EVENT_CH_1_RESULT

#define TR_HAL_ADC_EVENT_CH_1_RESULT   0x02

TR_HAL_ADC_EVENT_CH_2_RESULT

#define TR_HAL_ADC_EVENT_CH_2_RESULT   0x04

TR_HAL_ADC_EVENT_CH_3_RESULT

#define TR_HAL_ADC_EVENT_CH_3_RESULT   0x08

TR_HAL_ADC_EVENT_DMA

#define TR_HAL_ADC_EVENT_DMA   0x20

TR_HAL_ADC_INTERRUPT_ALL

#define TR_HAL_ADC_INTERRUPT_ALL   0x0FFFFF1D

TR_HAL_ADC_INTERRUPT_BASE

#define TR_HAL_ADC_INTERRUPT_BASE   0x0000001D

TR_HAL_ADC_INTERRUPT_CHAN_0

#define TR_HAL_ADC_INTERRUPT_CHAN_0   0x040000

TR_HAL_ADC_INTERRUPT_CHAN_1

#define TR_HAL_ADC_INTERRUPT_CHAN_1   0x080000

TR_HAL_ADC_INTERRUPT_CHAN_2

#define TR_HAL_ADC_INTERRUPT_CHAN_2   0x100000

TR_HAL_ADC_INTERRUPT_CHAN_3

#define TR_HAL_ADC_INTERRUPT_CHAN_3   0x200000

TR_HAL_ADC_INTERRUPT_DMA

#define TR_HAL_ADC_INTERRUPT_DMA   0x000001

TR_HAL_ADC_INTERRUPT_DONE

#define TR_HAL_ADC_INTERRUPT_DONE   0x000004

TR_HAL_ADC_INTERRUPT_HIGH_THRESH

#define TR_HAL_ADC_INTERRUPT_HIGH_THRESH   0x0FFC0000

TR_HAL_ADC_INTERRUPT_LOW_THRESH

#define TR_HAL_ADC_INTERRUPT_LOW_THRESH   0x0003FF00

TR_HAL_ADC_INTERRUPT_MODE_DONE

#define TR_HAL_ADC_INTERRUPT_MODE_DONE   0x000010

TR_HAL_ADC_INTERRUPT_VALID

#define TR_HAL_ADC_INTERRUPT_VALID   0x000008

TR_HAL_ADC_MAX_CLOCK_DIVISOR

#define TR_HAL_ADC_MAX_CLOCK_DIVISOR   65536

TR_HAL_ADC_MIN_CLOCK_DIVISOR

#define TR_HAL_ADC_MIN_CLOCK_DIVISOR   3

TR_HAL_ADC_R0_RESULT_MASK

#define TR_HAL_ADC_R0_RESULT_MASK   0x00003FFF

TR_HAL_ADC_R1_RESULT_MASK

#define TR_HAL_ADC_R1_RESULT_MASK   0x00000FFF

TR_HAL_ADC_R2_RESULT_MASK

#define TR_HAL_ADC_R2_RESULT_MASK   0x00000FFF

TR_HAL_ADC_THRESH_HIGH_DEFAULT

#define TR_HAL_ADC_THRESH_HIGH_DEFAULT   0x3FFF

TR_HAL_ADC_THRESH_LOW_DEFAULT

#define TR_HAL_ADC_THRESH_LOW_DEFAULT   0x0000

---

ADC threshholds

---

TR_HAL_NUM_ADC

#define TR_HAL_NUM_ADC   4

Typedef Documentation

tr_hal_adc_event_callback_t

typedef void(* tr_hal_adc_event_callback_t) (uint32_t raw_result, uint32_t converted_result, uint32_t event_bitmask, uint32_t int_status)

---

prototype for callback from the Trident HAL to the app when an event happens

---

tr_sadc_ana_set1_t

typedef union tr_sadc_ana_set1_s tr_sadc_ana_set1_t

---

this is taken from the chip sample code and is needed to setup the analog registers of the ADC

---

Enumeration Type Documentation

tr_hal_adc_channel_id_t

enum tr_hal_adc_channel_id_t

---

ADC IDs there are only 4 ADC channels since there are only 4 valid GPIOs to use

---

Enumerator
ADC_CHANNEL_0_ID
ADC_CHANNEL_1_ID
ADC_CHANNEL_2_ID
ADC_CHANNEL_3_ID

tr_hal_adc_clock_t

enum tr_hal_adc_clock_t

---

ADC clock to use

---

Enumerator
TR_HAL_ADC_USE_SYSTEM_CLOCK
TR_HAL_ADC_USE_SLOW_CLOCK

tr_hal_adc_mode_t

enum tr_hal_adc_mode_t

---

ADC mode

---

Enumerator
TR_HAL_ADC_MODE_ONE_SHOT
TR_HAL_ADC_MODE_TIMER
TR_HAL_ADC_MODE_SCAN

tr_hal_adc_oversample_t

enum tr_hal_adc_oversample_t

Enumerator
TR_HAL_ADC_REG_SAMPLE_NO_OVERSAMPLE
TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_2
TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_4
TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_8
TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_16
TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_32
TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_64
TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_128
TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_256

tr_hal_adc_pull_mode_t

enum tr_hal_adc_pull_mode_t

---

ADC pull mode

---

Enumerator
TR_HAL_ADC_PULL_LOW
TR_HAL_ADC_PULL_HIGH
TR_HAL_ADC_PULL_SINGLE_ENDED
TR_HAL_ADC_PULL_NOT_USED

tr_hal_adc_resolution_t

enum tr_hal_adc_resolution_t

---

ADC resolution (number of bits used)

---

Enumerator
TR_HAL_ADC_MODE_RESOLUTION_8_BIT
TR_HAL_ADC_MODE_RESOLUTION_10_BIT
TR_HAL_ADC_MODE_RESOLUTION_12_BIT
TR_HAL_ADC_MODE_RESOLUTION_14_BIT

tr_hal_time_t

enum tr_hal_time_t

---

ADC time - used for setting aquisition_time and end_delay_time

---

Enumerator
TR_HAL_ADC_TIME_HALF
TR_HAL_ADC_TIME_1
TR_HAL_ADC_TIME_2
TR_HAL_ADC_TIME_3
TR_HAL_ADC_TIME_4
TR_HAL_ADC_TIME_8
TR_HAL_ADC_TIME_12
TR_HAL_ADC_TIME_16