Collaboration diagram for SYSCTRL CM11:

Data Structures
struct	SYS_CTRL_REGISTERS_T
	offsets for where to find chip registers needed for System Control register which is used to configure GPIO pins (what mode are they in and pull up/down and open drain enable, etc see section 19.3 in the chip datasheet More...

Macros
#define	TR_HAL_NUM_PULL_REGISTERS 4
	defines for dealing with the SYS_CTRL pull registers, mode registers, and drive registers
#define	TR_HAL_PINS_PER_PULL_REG 8
#define	TR_HAL_NUM_MODE_REGISTERS 4
#define	TR_HAL_PINS_PER_MODE_REG 8
#define	TR_HAL_NUM_DRIVE_REGISTERS 2
#define	TR_HAL_PINS_PER_DRIVE_REG 16
#define	SYS_CTRL_CHIP_REGISTERS ((SYS_CTRL_REGISTERS_T *) CHIP_MEMORY_MAP_SYS_CTRL_BASE)
#define	SCC_UART0_CLOCK_BIT 16
#define	SCC_UART1_CLOCK_BIT 17
#define	SCC_UART2_CLOCK_BIT 18
#define	TR_HAL_ENABLE_LITE_SLEEP 1
#define	TR_HAL_ENABLE_DEEP_SLEEP 2

Detailed Description

Macro Definition Documentation

#define SCC_UART0_CLOCK_BIT 16

#define SCC_UART1_CLOCK_BIT 17

#define SCC_UART2_CLOCK_BIT 18

#define TR_HAL_ENABLE_DEEP_SLEEP 2

#define TR_HAL_ENABLE_LITE_SLEEP 1

#define TR_HAL_NUM_DRIVE_REGISTERS 2

#define TR_HAL_NUM_MODE_REGISTERS 4

#define TR_HAL_NUM_PULL_REGISTERS 4

defines for dealing with the SYS_CTRL pull registers, mode registers, and drive registers

#define TR_HAL_PINS_PER_DRIVE_REG 16

#define TR_HAL_PINS_PER_MODE_REG 8

#define TR_HAL_PINS_PER_PULL_REG 8