SYSCTRL CZ20

Collaboration diagram for SYSCTRL CZ20:

Data Structures
struct	SYS_CTRL_REGISTERS_T
	offsets for where to find chip registers needed for System Control register which is used to configure GPIO pins (what mode are they in and pull up/down and open drain enable, etc see section 19.3 in the chip datasheet More...

Macros
#define	TR_HAL_NUM_PULL_REGISTERS   4
	defines for dealing with the SYS_CTRL pull registers and drive registers
#define	TR_HAL_PINS_PER_PULL_REG   8
#define	TR_HAL_NUM_DRIVE_REGISTERS   2
#define	TR_HAL_PINS_PER_DRIVE_REG   16
#define	SYS_CTRL_HCLK_SELECT_XTAL_CLK   0x00
#define	SYS_CTRL_HCLK_SELECT_PLL_CLK   0x01
#define	SYS_CTRL_HCLK_SELECT_XTAL_CLK_DIV2   0x02
#define	SYS_CTRL_HCLK_SELECT_RCO_1M   0x03
#define	SYS_CTRL_HCLK_SELECT_MASK   0x03
#define	SYS_CTRL_PER_CLK_SELECT_XTAL_CLK   0x00
#define	SYS_CTRL_PER_CLK_SELECT_XTAL_CLK_DIV2   0x04
#define	SYS_CTRL_PER_CLK_SELECT_RCO_1M   0x08
#define	SYS_CTRL_PER_CLK_SELECT_MASK   0x0C
#define	SYS_CTRL_SLOW_CLK_SELECT_RCO_32K   0x00
#define	SYS_CTRL_SLOW_CLK_SELECT_XO_32K   0x40
#define	SYS_CTRL_SLOW_CLK_SELECT_EXTERNAL   0xC0
#define	SYS_CTRL_SLOW_CLK_SELECT_MASK   0xC0
#define	SYS_CTRL_BASEBAND_FREQ_48_MHZ   0x00
#define	SYS_CTRL_BASEBAND_FREQ_64_MHZ   0x100
#define	SYS_CTRL_BASEBAND_FREQ_36_MHZ   0x600
#define	SYS_CTRL_BASEBAND_FREQ_40_MHZ   0x700
#define	SYS_CTRL_BASEBAND_PLL_ENABLE   0x8000
#define	SYS_CTRL_BASEBAND_PLL_DISABLE   0x0000
#define	SYS_CTRL_UART_CLOCK_SELECT_PER_CLOCK   0x00
#define	SYS_CTRL_UART_CLOCK_SELECT_RCO_1M   0x02
#define	SYS_CTRL_UART_CLOCK_SELECT_RCO_32K   0x03
#define	SYS_CTRL_UART0_CLOCK_SELECT_BIT_SHIFT   0
#define	SYS_CTRL_UART1_CLOCK_SELECT_BIT_SHIFT   2
#define	SYS_CTRL_UART2_CLOCK_SELECT_BIT_SHIFT   4
#define	SYS_CTRL_SLOW_CLK_ENABLE_EXTERNAL   0x2000
#define	SYS_CTRL_SLOW_CLK_EXTERNAL_SRC_SHIFT   8
#define	SYS_CTRL_PWM_CLOCK_SELECT_HCLK   0x00
#define	SYS_CTRL_PWM_CLOCK_SELECT_PER_CLK   0x01
#define	SYS_CTRL_PWM_CLOCK_SELECT_RCO_1M   0x02
#define	SYS_CTRL_PWM_CLOCK_SELECT_SLOW_CLK   0x03
#define	SYS_CTRL_PWM0_CLOCK_SELECT_BIT_SHIFT   16
#define	SYS_CTRL_PWM1_CLOCK_SELECT_BIT_SHIFT   18
#define	SYS_CTRL_PWM2_CLOCK_SELECT_BIT_SHIFT   20
#define	SYS_CTRL_PWM3_CLOCK_SELECT_BIT_SHIFT   22
#define	SYS_CTRL_PWM4_CLOCK_SELECT_BIT_SHIFT   24
#define	SYS_CTRL_TIMER_CLOCK_SELECT_PER_CLK   0x00
#define	SYS_CTRL_TIMER_CLOCK_SELECT_RCO_1M   0x02
#define	SYS_CTRL_TIMER_CLOCK_SELECT_SLOW_CLK   0x03
#define	SYS_CTRL_TIMER0_CLOCK_SELECT_BIT_SHIFT   26
#define	SYS_CTRL_TIMER1_CLOCK_SELECT_BIT_SHIFT   28
#define	SYS_CTRL_TIMER2_CLOCK_SELECT_BIT_SHIFT   30
#define	TR_HAL_POWER_NORMAL   0x00
#define	TR_HAL_POWER_LITE_SLEEP   0x01
#define	TR_HAL_POWER_DEEP_SLEEP   0x02
#define	TR_HAL_POWER_POWERDOWN   0x04
#define	SYS_CTRL_CHIP_REGISTERS   ((SYS_CTRL_REGISTERS_T *) CHIP_MEMORY_MAP_SYS_CTRL_BASE)
#define	SCC_UART0_CLOCK_BIT   16
#define	SCC_UART1_CLOCK_BIT   17
#define	SCC_UART2_CLOCK_BIT   18

Detailed Description

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Macro Definition Documentation

SCC_UART0_CLOCK_BIT

#define SCC_UART0_CLOCK_BIT   16

SCC_UART1_CLOCK_BIT

#define SCC_UART1_CLOCK_BIT   17

SCC_UART2_CLOCK_BIT

#define SCC_UART2_CLOCK_BIT   18

SYS_CTRL_BASEBAND_FREQ_36_MHZ

#define SYS_CTRL_BASEBAND_FREQ_36_MHZ   0x600

SYS_CTRL_BASEBAND_FREQ_40_MHZ

#define SYS_CTRL_BASEBAND_FREQ_40_MHZ   0x700

SYS_CTRL_BASEBAND_FREQ_48_MHZ

#define SYS_CTRL_BASEBAND_FREQ_48_MHZ   0x00

SYS_CTRL_BASEBAND_FREQ_64_MHZ

#define SYS_CTRL_BASEBAND_FREQ_64_MHZ   0x100

SYS_CTRL_BASEBAND_PLL_DISABLE

#define SYS_CTRL_BASEBAND_PLL_DISABLE   0x0000

SYS_CTRL_BASEBAND_PLL_ENABLE

#define SYS_CTRL_BASEBAND_PLL_ENABLE   0x8000

SYS_CTRL_CHIP_REGISTERS

#define SYS_CTRL_CHIP_REGISTERS   ((SYS_CTRL_REGISTERS_T *) CHIP_MEMORY_MAP_SYS_CTRL_BASE)

SYS_CTRL_HCLK_SELECT_MASK

#define SYS_CTRL_HCLK_SELECT_MASK   0x03

SYS_CTRL_HCLK_SELECT_PLL_CLK

#define SYS_CTRL_HCLK_SELECT_PLL_CLK   0x01

SYS_CTRL_HCLK_SELECT_RCO_1M

#define SYS_CTRL_HCLK_SELECT_RCO_1M   0x03

SYS_CTRL_HCLK_SELECT_XTAL_CLK

#define SYS_CTRL_HCLK_SELECT_XTAL_CLK   0x00

SYS_CTRL_HCLK_SELECT_XTAL_CLK_DIV2

#define SYS_CTRL_HCLK_SELECT_XTAL_CLK_DIV2   0x02

SYS_CTRL_PER_CLK_SELECT_MASK

#define SYS_CTRL_PER_CLK_SELECT_MASK   0x0C

SYS_CTRL_PER_CLK_SELECT_RCO_1M

#define SYS_CTRL_PER_CLK_SELECT_RCO_1M   0x08

SYS_CTRL_PER_CLK_SELECT_XTAL_CLK

#define SYS_CTRL_PER_CLK_SELECT_XTAL_CLK   0x00

SYS_CTRL_PER_CLK_SELECT_XTAL_CLK_DIV2

#define SYS_CTRL_PER_CLK_SELECT_XTAL_CLK_DIV2   0x04

SYS_CTRL_PWM0_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_PWM0_CLOCK_SELECT_BIT_SHIFT   16

SYS_CTRL_PWM1_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_PWM1_CLOCK_SELECT_BIT_SHIFT   18

SYS_CTRL_PWM2_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_PWM2_CLOCK_SELECT_BIT_SHIFT   20

SYS_CTRL_PWM3_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_PWM3_CLOCK_SELECT_BIT_SHIFT   22

SYS_CTRL_PWM4_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_PWM4_CLOCK_SELECT_BIT_SHIFT   24

SYS_CTRL_PWM_CLOCK_SELECT_HCLK

#define SYS_CTRL_PWM_CLOCK_SELECT_HCLK   0x00

SYS_CTRL_PWM_CLOCK_SELECT_PER_CLK

#define SYS_CTRL_PWM_CLOCK_SELECT_PER_CLK   0x01

SYS_CTRL_PWM_CLOCK_SELECT_RCO_1M

#define SYS_CTRL_PWM_CLOCK_SELECT_RCO_1M   0x02

SYS_CTRL_PWM_CLOCK_SELECT_SLOW_CLK

#define SYS_CTRL_PWM_CLOCK_SELECT_SLOW_CLK   0x03

SYS_CTRL_SLOW_CLK_ENABLE_EXTERNAL

#define SYS_CTRL_SLOW_CLK_ENABLE_EXTERNAL   0x2000

SYS_CTRL_SLOW_CLK_EXTERNAL_SRC_SHIFT

#define SYS_CTRL_SLOW_CLK_EXTERNAL_SRC_SHIFT   8

SYS_CTRL_SLOW_CLK_SELECT_EXTERNAL

#define SYS_CTRL_SLOW_CLK_SELECT_EXTERNAL   0xC0

SYS_CTRL_SLOW_CLK_SELECT_MASK

#define SYS_CTRL_SLOW_CLK_SELECT_MASK   0xC0

SYS_CTRL_SLOW_CLK_SELECT_RCO_32K

#define SYS_CTRL_SLOW_CLK_SELECT_RCO_32K   0x00

SYS_CTRL_SLOW_CLK_SELECT_XO_32K

#define SYS_CTRL_SLOW_CLK_SELECT_XO_32K   0x40

SYS_CTRL_TIMER0_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_TIMER0_CLOCK_SELECT_BIT_SHIFT   26

SYS_CTRL_TIMER1_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_TIMER1_CLOCK_SELECT_BIT_SHIFT   28

SYS_CTRL_TIMER2_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_TIMER2_CLOCK_SELECT_BIT_SHIFT   30

SYS_CTRL_TIMER_CLOCK_SELECT_PER_CLK

#define SYS_CTRL_TIMER_CLOCK_SELECT_PER_CLK   0x00

SYS_CTRL_TIMER_CLOCK_SELECT_RCO_1M

#define SYS_CTRL_TIMER_CLOCK_SELECT_RCO_1M   0x02

SYS_CTRL_TIMER_CLOCK_SELECT_SLOW_CLK

#define SYS_CTRL_TIMER_CLOCK_SELECT_SLOW_CLK   0x03

SYS_CTRL_UART0_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_UART0_CLOCK_SELECT_BIT_SHIFT   0

SYS_CTRL_UART1_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_UART1_CLOCK_SELECT_BIT_SHIFT   2

SYS_CTRL_UART2_CLOCK_SELECT_BIT_SHIFT

#define SYS_CTRL_UART2_CLOCK_SELECT_BIT_SHIFT   4

SYS_CTRL_UART_CLOCK_SELECT_PER_CLOCK

#define SYS_CTRL_UART_CLOCK_SELECT_PER_CLOCK   0x00

SYS_CTRL_UART_CLOCK_SELECT_RCO_1M

#define SYS_CTRL_UART_CLOCK_SELECT_RCO_1M   0x02

SYS_CTRL_UART_CLOCK_SELECT_RCO_32K

#define SYS_CTRL_UART_CLOCK_SELECT_RCO_32K   0x03

TR_HAL_NUM_DRIVE_REGISTERS

#define TR_HAL_NUM_DRIVE_REGISTERS   2

TR_HAL_NUM_PULL_REGISTERS

#define TR_HAL_NUM_PULL_REGISTERS   4

defines for dealing with the SYS_CTRL pull registers and drive registers

---

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TR_HAL_PINS_PER_DRIVE_REG

#define TR_HAL_PINS_PER_DRIVE_REG   16

TR_HAL_PINS_PER_PULL_REG

#define TR_HAL_PINS_PER_PULL_REG   8

TR_HAL_POWER_DEEP_SLEEP

#define TR_HAL_POWER_DEEP_SLEEP   0x02

TR_HAL_POWER_LITE_SLEEP

#define TR_HAL_POWER_LITE_SLEEP   0x01

TR_HAL_POWER_NORMAL

#define TR_HAL_POWER_NORMAL   0x00

TR_HAL_POWER_POWERDOWN

#define TR_HAL_POWER_POWERDOWN   0x04