TRNG CZ20

Collaboration diagram for TRNG CZ20:

Data Structures
struct	SECURITY_CTRL_REGISTERS_T
struct	TRNG_REGISTERS_T

Macros
#define	CHIP_MEMORY_MAP_SECURITY_CTRL_BASE   0x50003000
#define	SECURITY_CTRL_CHIP_REGISTERS   ((SECURITY_CTRL_REGISTERS_T *) CHIP_MEMORY_MAP_SECURITY_CTRL_BASE)
#define	OTP_WRITE_ENABLE_KEY   (0x28514260)
#define	OTP_WRITE_DISABLE_KEY   (0x00000000)
#define	CHIP_MEMORY_MAP_TRNG_BASE   (0x40044A00UL)
	chip register addresses section 2.2 of the data sheet explains the Memory map. this gives the base address for how to write the chip registers the chip registers are how the software interacts configures GPIOs, reads GPIOs, and gets/sets information on the chip We create a struct below that addresses the individual registers. This makes it so we can use this base address and a struct field to read or write a chip register
#define	REG_TRNG_EXPECTED_VERSION   0x39304200
#define	REG_TRNG_STATUS_BUSY   0x01
#define	REG_TRNG_STATUS_FIFO_CLEARED   0x02
#define	REG_TRNG_STATUS_ENTROPY_SRC_AVAIL   0x04
#define	REG_TRNG_STATUS_NOT_ENABLED   0x100
#define	REG_TRNG_STATUS_HEALTH_TEST_ACTIVE   0x200
#define	REG_TRNG_STATUS_DATA_READY   0x400
#define	REG_TRNG_STATUS_HALTED_ERROR   0x800
#define	REG_CONTROL_ENABLE_TRNG_FUNCTION   0x01
#define	REG_CONTROL_ENABLE_TRNG_CLOCK   0x02
#define	TRNG_CHIP_REGISTERS   ((TRNG_REGISTERS_T *) CHIP_MEMORY_MAP_TRNG_BASE)
#define	TRNG_TIMEOUT_COUNT   20000

Functions
tr_hal_status_t	tr_hal_trng_read_internal (uint32_t *result, uint32_t *busy_cycles)
tr_hal_status_t	tr_hal_trng_debug (uint32_t *version, uint32_t *status, uint32_t *data, uint32_t *control)

Detailed Description

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Macro Definition Documentation

CHIP_MEMORY_MAP_SECURITY_CTRL_BASE

#define CHIP_MEMORY_MAP_SECURITY_CTRL_BASE   0x50003000

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security control register

we need this register since the first time the TRNG gets run it needs to enable the TRNG and to do that it needs to have write access which it can only get by setting the write access key_comp in register sec_otp_write_key. This may eventually move to another module

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CHIP_MEMORY_MAP_TRNG_BASE

#define CHIP_MEMORY_MAP_TRNG_BASE   (0x40044A00UL)

chip register addresses section 2.2 of the data sheet explains the Memory map. this gives the base address for how to write the chip registers the chip registers are how the software interacts configures GPIOs, reads GPIOs, and gets/sets information on the chip We create a struct below that addresses the individual registers. This makes it so we can use this base address and a struct field to read or write a chip register

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OTP_WRITE_DISABLE_KEY

#define OTP_WRITE_DISABLE_KEY   (0x00000000)

OTP_WRITE_ENABLE_KEY

#define OTP_WRITE_ENABLE_KEY   (0x28514260)

REG_CONTROL_ENABLE_TRNG_CLOCK

#define REG_CONTROL_ENABLE_TRNG_CLOCK   0x02

REG_CONTROL_ENABLE_TRNG_FUNCTION

#define REG_CONTROL_ENABLE_TRNG_FUNCTION   0x01

REG_TRNG_EXPECTED_VERSION

#define REG_TRNG_EXPECTED_VERSION   0x39304200

REG_TRNG_STATUS_BUSY

#define REG_TRNG_STATUS_BUSY   0x01

REG_TRNG_STATUS_DATA_READY

#define REG_TRNG_STATUS_DATA_READY   0x400

REG_TRNG_STATUS_ENTROPY_SRC_AVAIL

#define REG_TRNG_STATUS_ENTROPY_SRC_AVAIL   0x04

REG_TRNG_STATUS_FIFO_CLEARED

#define REG_TRNG_STATUS_FIFO_CLEARED   0x02

REG_TRNG_STATUS_HALTED_ERROR

#define REG_TRNG_STATUS_HALTED_ERROR   0x800

REG_TRNG_STATUS_HEALTH_TEST_ACTIVE

#define REG_TRNG_STATUS_HEALTH_TEST_ACTIVE   0x200

REG_TRNG_STATUS_NOT_ENABLED

#define REG_TRNG_STATUS_NOT_ENABLED   0x100

SECURITY_CTRL_CHIP_REGISTERS

#define SECURITY_CTRL_CHIP_REGISTERS   ((SECURITY_CTRL_REGISTERS_T *) CHIP_MEMORY_MAP_SECURITY_CTRL_BASE)

TRNG_CHIP_REGISTERS

#define TRNG_CHIP_REGISTERS   ((TRNG_REGISTERS_T *) CHIP_MEMORY_MAP_TRNG_BASE)

TRNG_TIMEOUT_COUNT

#define TRNG_TIMEOUT_COUNT   20000

Function Documentation

tr_hal_trng_debug()

tr_hal_status_t tr_hal_trng_debug	(	uint32_t *	version,
		uint32_t *	status,
		uint32_t *	data,
		uint32_t *	control )

tr_hal_trng_read_internal()

tr_hal_status_t tr_hal_trng_read_internal	(	uint32_t *	result,
		uint32_t *	busy_cycles )