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Trident IoT SDK
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Trident IoT SDK
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Collaboration diagram for UART CM11:Data Structures | |
| struct | UART_REGISTERS_T |
| struct | tr_hal_uart_settings_t |
Typedefs | |
| typedef void(* | tr_hal_uart_receive_callback_t) (uint8_t received_byte) |
| typedef void(* | tr_hal_uart_event_callback_t) (uint32_t event_bitmask) |
Functions | |
| UART_REGISTERS_T * | tr_hal_uart_get_uart_register_address (tr_hal_uart_id_t uart_id) |
| #define CHIP_MEMORY_MAP_UART0_BASE (0xA0000000UL) |
section 3.1 of the data sheet explains the Memory map this gives the base address for how to write the UART registers the UART registers are how the software interacts with the UART peripheral. We create a struct below that addresses the individual registers. This makes it so we can use this base address and a struct field to read or write a chip register
| #define CHIP_MEMORY_MAP_UART1_BASE (0xA0500000UL) |
| #define CHIP_MEMORY_MAP_UART2_BASE (0xA0600000UL) |
| #define DEFAULT_UART0_CONFIG |
| #define DEFAULT_UART1_CONFIG |
| #define DEFAULT_UART2_CONFIG |
| #define divisor_latch_LSB receive_buffer_register |
| #define divisor_latch_MSB interrupt_enable_register |
| #define DMA_IER_ENABLE_RECEIVE_INT 0x01 |
| #define DMA_IER_ENABLE_TRANSMIT_INT 0x02 |
| #define DMA_RECEIVE_INTERRUPT 0x01 |
| #define DMA_RX_BUFF_MINIMUM_SIZE 16 |
| #define DMA_TRANSMIT_INTERRUPT 0x02 |
| #define FCR_CLEAR_RECEIVER 0x02 |
| #define FCR_CLEAR_TRANSMIT 0x04 |
| #define FCR_DMA_SELECT 0x08 |
| #define FCR_FIFO_ENABLE 0x01 |
| #define FCR_TRIGGER_MASK 0xC0 |
| #define IER_ENABLE_FRAMING_PARITY_OVERRUN_ERROR_INT 0x04 |
| #define IER_ENABLE_MODEM_STATUS_INT 0x08 |
| #define IER_ENABLE_READY_TO_TRANSMIT_INT 0x02 |
| #define IER_ENABLE_RECEIVE_DATA_AVAIL_INT 0x01 |
| #define IIR_CHAR_TIMEOUT_INTERRUPT 0x0C |
| #define IIR_INTERRUPT_MASK 0x0F |
| #define IIR_MODEM_STATUS_INTERRUPT 0x00 |
| #define IIR_NO_INTERRUPT_PENDING 0x01 |
| #define IIR_RECEIVER_ERROR_INTERRUPT 0x06 |
| #define IIR_RX_DATA_AVAIL_INTERRUPT 0x04 |
| #define IIR_THR_EMPTY_INTERRUPT 0x02 |
| #define interrupt_identification_register FIFO_control_register |
| #define LCR_BAUD_RATE_SETTING_MASK 0x80 |
| #define LCR_DATA_BITS_INV_MASK 0xFC |
| #define LCR_DATA_BITS_MASK 0x03 |
| #define LCR_PARITY_BITS_INV_MASK 0xE7 |
| #define LCR_PARITY_BITS_MASK 0x18 |
| #define LCR_STOP_BITS_INV_MASK 0xFB |
| #define LCR_STOP_BITS_MASK 0x04 |
| #define LOW_BYTES_BUFFER_THRESHHOLD 16 |
| #define LSR_BREAK_INDICATOR 0x10 |
| #define LSR_DATA_READY 0x01 |
| #define LSR_FIFO_ERROR 0x80 |
| #define LSR_FRAMING_ERROR 0x08 |
| #define LSR_OVERRUN_ERROR 0x02 |
| #define LSR_PARITY_ERROR 0x04 |
| #define LSR_TRANSMITTER_EMPTY 0x40 |
| #define LSR_TRANSMITTER_HOLDING_REG_EMPTY 0x20 |
| #define MAX_RAW_TX_DATA_BUFFER_SIZE 256 |
| #define MSR_CTS 0x10 |
| #define MSR_DCD 0x80 |
| #define MSR_DCTS 0x01 |
| #define MSR_DDCD 0x08 |
| #define MSR_DDSR 0x02 |
| #define MSR_DSR 0x20 |
| #define MSR_RI 0x40 |
| #define MSR_TERI 0x04 |
| #define TR_HAL_PIN_NOT_SET 255 |
| #define TR_HAL_UART_EVENT_DMA_RX_BUFFER_LOW 0x00000002 |
| #define TR_HAL_UART_EVENT_DMA_RX_READY 0x00000008 |
| #define TR_HAL_UART_EVENT_DMA_RX_TO_USER_FX 0x00000004 |
| #define TR_HAL_UART_EVENT_DMA_TX_COMPLETE 0x00000001 |
these are the EVENTS that can be received into the UART event handler functions. These are BITMASKs since we can have more than 1 in an event these are what the APP needs to handle in its event_handler_fx
| #define TR_HAL_UART_EVENT_HW_FLOW_CONTROL 0x00008000 |
| #define TR_HAL_UART_EVENT_RX_ENDED_NO_DATA 0x00000200 |
| #define TR_HAL_UART_EVENT_RX_ENDED_TO_USER_FX 0x00000100 |
| #define TR_HAL_UART_EVENT_RX_ERR_BREAK 0x00004000 |
| #define TR_HAL_UART_EVENT_RX_ERR_FRAMING 0x00002000 |
| #define TR_HAL_UART_EVENT_RX_ERR_OVERRUN 0x00000800 |
| #define TR_HAL_UART_EVENT_RX_ERR_PARITY 0x00001000 |
| #define TR_HAL_UART_EVENT_RX_MAYBE_READY 0x00000400 |
| #define TR_HAL_UART_EVENT_RX_READY 0x00000080 |
| #define TR_HAL_UART_EVENT_RX_TO_USER_FX 0x00000040 |
| #define TR_HAL_UART_EVENT_TX_COMPLETE 0x00000010 |
| #define TR_HAL_UART_EVENT_TX_STILL_GOING 0x00000020 |
| #define TR_HAL_UART_EVENT_UNEXPECTED 0x00010000 |
| #define TR_NUMBER_OF_UARTS 3 |
defines used by the UART module
| #define transmitter_holding_register receive_buffer_register |
| #define TX_FIFO_SIZE 16 |
| #define UART0_CHIP_REGISTERS ((UART_REGISTERS_T *) CHIP_MEMORY_MAP_UART0_BASE) |
| #define UART0_RX_PIN_OPTION1 16 |
| #define UART0_TX_PIN_OPTION1 17 |
| #define UART1_CHIP_REGISTERS ((UART_REGISTERS_T *) CHIP_MEMORY_MAP_UART1_BASE) |
| #define UART1_CTS_PIN_OPTION1 15 |
| #define UART1_CTS_PIN_OPTION2 21 |
| #define UART1_RTS_PIN_OPTION1 14 |
| #define UART1_RTS_PIN_OPTION2 20 |
| #define UART1_RX_PIN_OPTION1 5 |
| #define UART1_RX_PIN_OPTION3 29 |
| #define UART1_TX_PIN_OPTION1 4 |
| #define UART1_TX_PIN_OPTION3 28 |
| #define UART2_CHIP_REGISTERS ((UART_REGISTERS_T *) CHIP_MEMORY_MAP_UART2_BASE) |
| #define UART2_RX_PIN_OPTION1 7 |
| #define UART2_RX_PIN_OPTION3 31 |
| #define UART2_TX_PIN_OPTION1 6 |
| #define UART2_TX_PIN_OPTION3 30 |
| #define UART_DMA_DISABLE 0x00 |
| #define UART_DMA_ENABLE 0x01 |
| #define UART_INVALID_PIN 0xFF |
Pin information for the 3 UARTs of the T32CM11
UART valid pin configurations are below
PIN_17 = UART_0_TX PIN_16 = UART_0_RX
PIN_4 or PIN_28 = UART_1_TX (note PIN_10 is normally a choice but not on this chip) PIN_5 or PIN_29 = UART_1_RX (note PIN_11 is normally a choice but not on this chip)
PIN_14 or PIN_20 or PIN_18 = UART_1_RTSN PIN_15 or PIN_21 or PIN_19 = UART_1_CTSN
PIN_6 or PIN_30 = UART_2_TX (note PIN_12 is normally a choice but not on this chip) PIN_7 or PIN_31 = UART_2_RX (note PIN_13 is normally a choice but not on this chip)
| typedef void(* tr_hal_uart_event_callback_t) (uint32_t event_bitmask) |
| typedef void(* tr_hal_uart_receive_callback_t) (uint8_t received_byte) |
| enum tr_hal_baud_rate_t |
| enum tr_hal_data_bits_t |
| enum tr_hal_hw_fc_t |
| enum tr_hal_parity_t |
| enum tr_hal_stop_bits_t |
| enum tr_hal_uart_id_t |
| UART_REGISTERS_T * tr_hal_uart_get_uart_register_address | ( | tr_hal_uart_id_t | uart_id | ) |
if the app wants to directly interface with the chip registers, this is a convenience function for getting the address/struct of a particular UART so the chip registers can be accessed.
EXAMPLE: check LSR and if ready, read a byte from RBR
UART_REGISTERS_T* uart_register_address = tr_hal_uart_get_uart_register_address(2);
if ((uart_register_address->line_status_register) & LSR_DATA_READY)
{
uint8_t rx_data = uart_register_address->receive_buffer_register;
}
1.10.0