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partition.h
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1
2#ifndef _PARTITION_RT584_CM33_H_
3#define _PARTITION_RT584_CM33_H_
4
5#include "cm33.h"
6
7/*
8* Flash Size Information Address
9*
10*
11*
12*/
13#define FLASH_SIZE_INFO 0x50009038
14/*
15* <e>Setup behaviour of Sleep and Exception Handling
16*/
17#define SCB_CSR_AIRCR_INIT 1
18
19/*
20* <o> Deep Sleep can be enabled by
21* <0=>Secure and Non-Secure state
22* <1=>Secure state only
23* <i> Value for SCB->CSR register bit DEEPSLEEPS
24*/
25#define SCB_CSR_DEEPSLEEPS_VAL 0
26
27/*
28* <o>System reset request accessible from
29* <0=> Secure and Non-Secure state
30* <1=> Secure state only
31* <i> Value for SCB->AIRCR register bit SYSRESETREQS
32*/
33#define SCB_AIRCR_SYSRESETREQS_VAL 0
34
35/*
36* <o>Priority of Non-Secure exceptions is
37* <0=> Not altered
38* <1=> Lowered to 0x80-0xFF
39* <i> Value for SCB->AIRCR register bit PRIS
40*/
41#define SCB_AIRCR_PRIS_VAL 1
42
43/*
44* <o>BusFault, HardFault, and NMI target
45* <0=> Secure state
46* <1=> Non-Secure state
47* <i> Value for SCB->AIRCR register bit BFHFNMINS
48*/
49#define SCB_AIRCR_BFHFNMINS_VAL 0
50
51/*
52* </e>
53*/
54
55/*
56* <e>Setup behaviour of Floating Point Unit
57*/
58#define TZ_FPU_NS_USAGE 1
59
60/*
61* <o>Floating Point Unit usage
62* <0=> Secure state only
63* <3=> Secure and Non-Secure state
64* <i> Value for SCB->NSACR register bits CP10, CP11
65*/
66#define SCB_NSACR_CP10_11_VAL 3
67
68/*
69* <o>Treat floating-point registers as Secure
70* <0=> Disabled
71* <1=> Enabled
72* <i> Value for FPU->FPCCR register bit TS
73*/
74#define FPU_FPCCR_TS_VAL 0
75
76/*
77* <o>Clear on return (CLRONRET) accessibility
78* <0=> Secure and Non-Secure state
79* <1=> Secure state only
80* <i> Value for FPU->FPCCR register bit CLRONRETS
81*/
82#define FPU_FPCCR_CLRONRETS_VAL 0
83
84/*
85* <o>Clear floating-point caller saved registers on exception return
86* <0=> Disabled
87* <1=> Enabled
88* <i> Value for FPU->FPCCR register bit CLRONRET
89*/
90#define FPU_FPCCR_CLRONRET_VAL 1
91
92#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
101__STATIC_INLINE uint32_t SEC_GetIADUState(SEC_IADU_Type SecIADUn)
102{
103 if ((int32_t)(SecIADUn) >= 0)
104 {
105 return ((uint32_t)(((SEC_CTRL->SEC_PERI_ATTR[(((uint32_t)SecIADUn) >> 5UL)] & (1UL << (((uint32_t)SecIADUn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
106 }
107 else
108 {
109 return (0U);
110 }
111}
112
113
122__STATIC_INLINE uint32_t SEC_SetIADUState(SEC_IADU_Type SecIADUn)
123{
124 if ((int32_t)(SecIADUn) >= 0)
125 {
126 SEC_CTRL->SEC_PERI_ATTR[(((uint32_t)SecIADUn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)SecIADUn) & 0x1FUL)));
127 return ((uint32_t)(((SEC_CTRL->SEC_PERI_ATTR[(((uint32_t)SecIADUn) >> 5UL)] & (1UL << (((uint32_t)SecIADUn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
128 }
129 else
130 {
131 return (0U);
132 }
133}
134
135
144__STATIC_INLINE uint32_t SEC_ClearIADUState(SEC_IADU_Type SecIADUn)
145{
146
147 if ((int32_t)(SecIADUn) >= 0)
148 {
149 SEC_CTRL->SEC_PERI_ATTR[(((uint32_t)SecIADUn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)SecIADUn) & 0x1FUL)));
150 return ((uint32_t)(((SEC_CTRL->SEC_PERI_ATTR[(((uint32_t)SecIADUn) >> 5UL)] & (1UL << (((uint32_t)SecIADUn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
151 }
152 else
153 {
154 return (0U);
155 }
156}
157
158#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
159
160
161__STATIC_INLINE void TZ_SAU_Setup (void)
162{
163
164 uint32_t flash_model_info;
165 uint32_t flash_size;
166
167#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
168 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
169 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
170
171 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
172 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
173 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
174 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
175 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
176 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
177#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
178
179#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
180 defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
181
182 SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
183 ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
184
185 FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
186 ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
187 ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
188 ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
189#endif
190
191
192
193 TZ_SAU_Disable();
194
195
196
197 flash_model_info = inp32((((void *)FLASH) + 0x38));
198 flash_size = (1 << ((flash_model_info >> 16) & 0xFF));
199 flash_size = (flash_size >> 5); /*32 bytes uints*/
200
201 /*set the whole flash as non-secure first in bootrom time*/
202 /*set the sram to be secure during bootrom time*/
203 /*set all flash in secure mode*/
204 SEC_CTRL->SEC_FLASH_SEC_SIZE = 0x8000;
205 SEC_CTRL->SEC_FLASH_NSC_START = 0x8000;
206 SEC_CTRL->SEC_FLASH_NSC_STOP = 0x8000;
207 SEC_CTRL->SEC_FLASH_NS_STOP = flash_size;
208
209 /*
210 * Here assume 64KB secure... NSC in 62KB. 0x400 bytes.
211 * Sec address Non Sec address
212 * RAM0 0x30000000 0x30007FFF 32KB RAM0 0x20000000 0x20007FFF 32KB
213 * RAM1 0x30008000 0x3000FFFF 32KB RAM1 0x20008000 0x2000FFFF 32KB
214 * RAM2 0x30010000 0x30017FFF 32KB RAM2 0x20010000 0x20017FFF 32KB
215 * RAM3 0x30018000 0x3001FFFF 32KB RAM3 0x20018000 0x2001FFFF 32KB
216 * RAM4 0x30020000 0x30027FFF 32KB RAM4 0x20020000 0x20027FFF 32KB
217 * RAM5 0x30028000 0x3002BFFF 16KB RAM5 0x20028000 0x2002BFFF 16KB
218 * RAM6 0x3002C000 0x3002FFFF 16KB RAM6 0x2002C000 0x2002FFFF 16KB
219 *
220 * set the sram to be secure during bootrom time
221 * For bootrom we set all SRAM (64KB as secure).
222 * NO NSC in SRAM. so SEC_RAM_NSC_START = SEC_RAM_NSC_STOP
223 */
224 SEC_CTRL->SEC_RAM_SEC_SIZE = 0x1800; /* 0x30010000 (0x30000000 + sec_ram_s_stop*32-1)--> 0x800*32 --> 10000 (64K) 0x30000000~0x3000FFFF*/
225 SEC_CTRL->SEC_RAM_NSC_START = 0x1800; /* 0x3000F7FF (0x30000000 + sec_ram_nsc_start*32-1) 0x7C0*32 --> F7FF*/
226 SEC_CTRL->SEC_RAM_NSC_STOP = 0x1800; /* 0x3000FBFF (0x30000000 + sec_ram_nsc_start*32-1) 0x7E0*32 --> FBFF*/
227
228 /****** rt584_CM33 Specific Sec attribuite Numbers *************************************************/
229 //SEC_ClearIADUState(SEC_IADU_Type); secure
230 //SEC_SetIADUState(SEC_IADU_Type); non-secure,
231 //* 1 is non-secure, 0 is secure.
232 //SEC_ClearIADUState function config interrupt to sec world
233 //Attribuite 0
234#if (SYSCTRL_SECURE_EN == 1)
235 SEC_ClearIADUState(SYS_CTRL_IADU_Type);
236#else
237 SEC_SetIADUState(SYS_CTRL_IADU_Type);
238#endif
239
240#if (GPIO_SECURE_EN == 1)
241 SEC_ClearIADUState(GPIO_IADU_Type);
242#else
243 SEC_SetIADUState(GPIO_IADU_Type);
244#endif
245
246#if (RTC_SECURE_EN == 1)
247 SEC_ClearIADUState(RTC_IADU_Type);
248#else
249 SEC_SetIADUState(RTC_IADU_Type);
250#endif
251
252#if (DPD_SECURE_EN == 1)
253 SEC_ClearIADUState(DPD_CTRL_IADU_Type);
254#else
255 SEC_SetIADUState(DPD_CTRL_IADU_Type);
256#endif
257
258#if (SOC_PMU_SECURE_EN == 1)
259 SEC_ClearIADUState(SOC_PMU_IADU_Type);
260#else
261 SEC_SetIADUState(SOC_PMU_IADU_Type);
262#endif
263
264#if (FLASHCTRL_SECURE_EN == 1)
265 SEC_ClearIADUState(FLASH_CONTROL_IADU_Type);
266#else
267 SEC_SetIADUState(FLASH_CONTROL_IADU_Type);
268#endif
269
270#if (TIMER0_SECURE_EN == 1)
271 SEC_ClearIADUState(TIMER0_IADU_Type);
272#else
273 SEC_SetIADUState(TIMER0_IADU_Type);
274#endif
275
276#if (TIMER1_SECURE_EN == 1)
277 SEC_ClearIADUState(TIMER1_IADU_Type);
278#else
279 SEC_SetIADUState(TIMER1_IADU_Type);
280#endif
281
282#if (TIMER2_SECURE_EN == 1)
283 SEC_ClearIADUState(TIMER2_IADU_Type);
284#else
285 SEC_SetIADUState(TIMER2_IADU_Type);
286#endif
287
288#if (TIMER32K0_SECURE_EN == 1)
289 SEC_ClearIADUState(TIMER32K0_IADU_Type);
290#else
291 SEC_SetIADUState(TIMER32K0_IADU_Type);
292#endif
293
294#if (TIMER32K1_SECURE_EN == 1)
295 SEC_ClearIADUState(TIMER32K1_IADU_Type);
296#else
297 SEC_SetIADUState(TIMER32K1_IADU_Type);
298#endif
299
300#if (WDT_SECURE_EN == 1)
301 SEC_ClearIADUState(WDT_IADU_Type);
302#else
303 SEC_SetIADUState(WDT_IADU_Type);
304#endif
305
306#if (UART0_SECURE_EN == 1)
307 SEC_ClearIADUState(UART0_IADU_Type);
308#else
309 SEC_SetIADUState(UART0_IADU_Type);
310#endif
311
312#if (UART1_SECURE_EN == 1)
313 SEC_ClearIADUState(UART1_IADU_Type);
314#else
315 SEC_SetIADUState(UART1_IADU_Type);
316#endif
317
318#if (I2C_SLAVE_SECURE_EN == 1)
319 SEC_ClearIADUState(I2C_S_IADU_Type);
320#else
321 SEC_SetIADUState(I2C_S_IADU_Type);
322#endif
323
324#if (COMM_SUBSYSTEM_AHB_SECURE_EN == 1)
325 SEC_ClearIADUState(RT569_AHB_IADU_Type);
326#else
327 SEC_SetIADUState(RT569_AHB_IADU_Type);
328#endif
329
330#if (RCO32K_CAL_SECURE_EN == 1)
331 SEC_ClearIADUState(RCO32K_CAL_IADU_Type);
332#else
333 SEC_SetIADUState(RCO32K_CAL_IADU_Type);
334#endif
335
336#if (BOD_COMP_SECURE_EN == 1)
337 SEC_ClearIADUState(BOD_COMP_IADU_Type);
338#else
339 SEC_SetIADUState(BOD_COMP_IADU_Type);
340#endif
341
342#if (AUX_COMP_SECURE_EN == 1)
343 SEC_ClearIADUState(AUX_COMP_IADU_Type);
344#else
345 SEC_SetIADUState(AUX_COMP_IADU_Type);
346#endif
347
348#if (RCO1M_CAL_SECURE_EN == 1)
349 SEC_ClearIADUState(RCO1M_CAL_IADU_Type);
350#else
351 SEC_SetIADUState(RCO1M_CAL_IADU_Type);
352#endif
353
354
355 //Attribuite 1
356#if (QSPI0_SECURE_EN == 1)
357 SEC_ClearIADUState(QSPI0_IADU_Type);
358#else
359 SEC_SetIADUState(QSPI0_IADU_Type);
360#endif
361
362#if (QSPI1_SECURE_EN == 1)
363 SEC_ClearIADUState(QSPI1_IADU_Type);
364#else
365 SEC_SetIADUState(QSPI1_IADU_Type);
366#endif
367
368#if (IRM_SECURE_EN == 1)
369 SEC_ClearIADUState(IRM_IADU_Type);
370#else
371 SEC_SetIADUState(IRM_IADU_Type);
372#endif
373
374#if (UART2_SECURE_EN == 1)
375 SEC_ClearIADUState(UART2_IADU_Type);
376#else
377 SEC_SetIADUState(UART2_IADU_Type);
378#endif
379
380#if (PWM_SECURE_EN == 1)
381 SEC_ClearIADUState(PWM_IADU_Type);
382#else
383 SEC_SetIADUState(PWM_IADU_Type);
384#endif
385
386#if (XDMA_SECURE_EN == 1)
387 SEC_ClearIADUState(XDMA_IADU_Type);
388#else
389 SEC_SetIADUState(XDMA_IADU_Type);
390#endif
391
392#if (DMA0_SECURE_EN == 1)
393 SEC_ClearIADUState(DMA0_IADU_Type);
394#else
395 SEC_SetIADUState(DMA0_IADU_Type);
396#endif
397
398#if (DMA1_SECURE_EN == 1)
399 SEC_ClearIADUState(DMA1_IADU_Type);
400#else
401 SEC_SetIADUState(DMA1_IADU_Type);
402#endif
403
404#if (I2C_MASTER0_SECURE_EN == 1)
405 SEC_ClearIADUState(I2C_M0_IADU_Type);
406#else
407 SEC_SetIADUState(I2C_M0_IADU_Type);
408#endif
409
410#if (I2C_MASTER1_SECURE_EN == 1)
411 SEC_ClearIADUState(I2C_M1_IADU_Type);
412#else
413 SEC_SetIADUState(I2C_M1_IADU_Type);
414#endif
415
416#if (I2S0_SECURE_EN == 1)
417 SEC_ClearIADUState(I2S0_M_IADU_Type);
418#else
419 SEC_SetIADUState(I2S0_M_IADU_Type);
420#endif
421
422#if (SADC_SECURE_EN == 1)
423 SEC_ClearIADUState(SADC_IADU_Type);
424#else
425 SEC_SetIADUState(SADC_IADU_Type);
426#endif
427
428#if (SW_IRQ0_SECURE_EN == 1)
429 SEC_ClearIADUState(SW_IRQ0_IADU_Type);
430#else
431 SEC_SetIADUState(SW_IRQ0_IADU_Type);
432#endif
433
434#if (SW_IRQ1_SECURE_EN == 1)
435 SEC_ClearIADUState(SW_IRQ1_IADU_Type);
436#else
437 SEC_SetIADUState(SW_IRQ1_IADU_Type);
438#endif
439
440
441 //Attribuite 2
442#if (CRYPTO_SECURE_EN == 1)
443 SEC_ClearIADUState(CRYPTO_IADU_Type);
444#else
445 SEC_SetIADUState(CRYPTO_IADU_Type);
446#endif
447
448#if (PUF_OTP_SECURE_EN == 1)
449 SEC_ClearIADUState(PUF_OTP_IADU_Type);
450#else
451 SEC_SetIADUState(PUF_OTP_IADU_Type);
452#endif
453 //SEC_SetIADUState function config interrupt to non sec world
454
455
456 /****** rt584 cm33S pecific Interrupt Numbers *************************************************/
457 //NVIC_ClearTargetState(IQRn_Type); secure
458 //NVIC_SetTargetState(IQRn_Type); no secure
459 //Nvic ClearTargeStat function config interrupt to sec world
460 NVIC_ClearTargetState(Sec_Ctrl_IQRn);
461 //Attribuite 0
462#if (GPIO_SECURE_EN == 1)
463 NVIC_ClearTargetState(Gpio_IRQn);
464#else
465 NVIC_SetTargetState(Gpio_IRQn);
466#endif
467
468#if (RTC_SECURE_EN == 1)
469 NVIC_ClearTargetState(Rtc_IRQn);
470#else
471 NVIC_SetTargetState(Rtc_IRQn);
472#endif
473
474#if (FLASHCTRL_SECURE_EN == 1)
475 NVIC_ClearTargetState(FlashCtl_IRQn);
476#else
477 NVIC_SetTargetState(FlashCtl_IRQn);
478#endif
479
480#if (TIMER0_SECURE_EN == 1)
481 NVIC_ClearTargetState(Timer0_IRQn);
482#else
483 NVIC_SetTargetState(Timer0_IRQn);
484#endif
485
486#if (TIMER1_SECURE_EN == 1)
487 NVIC_ClearTargetState(Timer1_IRQn);
488#else
489 NVIC_SetTargetState(Timer1_IRQn);
490#endif
491
492#if (TIMER2_SECURE_EN == 1)
493 NVIC_ClearTargetState(Timer2_IRQn);
494#else
495 NVIC_SetTargetState(Timer2_IRQn);
496#endif
497
498#if (TIMER32K0_SECURE_EN == 1)
499 NVIC_ClearTargetState(Timer32K0_IRQn);
500#else
501 NVIC_SetTargetState(Timer32K0_IRQn);
502#endif
503
504#if (TIMER32K1_SECURE_EN == 1)
505 NVIC_ClearTargetState(Timer32K1_IRQn);
506#else
507 NVIC_SetTargetState(Timer32K1_IRQn);
508#endif
509
510#if (WDT_SECURE_EN == 1)
511 NVIC_ClearTargetState(Wdt_IRQn);
512#else
513 NVIC_SetTargetState(Wdt_IRQn);
514#endif
515
516#if (UART0_SECURE_EN == 1)
517 NVIC_ClearTargetState(Uart0_IRQn);
518#else
519 NVIC_SetTargetState(Uart0_IRQn);
520#endif
521
522#if (UART1_SECURE_EN == 1)
523 NVIC_ClearTargetState(Uart1_IRQn);
524#else
525 NVIC_SetTargetState(Uart1_IRQn);
526#endif
527
528#if (I2C_SLAVE_SECURE_EN == 1)
529 NVIC_ClearTargetState(I2C_Slave_IRQn);
530#else
531 NVIC_SetTargetState(I2C_Slave_IRQn);
532#endif
533
534#if (COMM_SUBSYSTEM_AHB_SECURE_EN == 1)
535 NVIC_ClearTargetState(CommSubsystem_IRQn);
536#else
537 NVIC_SetTargetState(CommSubsystem_IRQn);
538#endif
539
540#if (BOD_COMP_SECURE_EN == 1)
541 NVIC_ClearTargetState(Bod_Comp_IRQn);
542#else
543 NVIC_SetTargetState(Bod_Comp_IRQn);
544#endif
545
546#if (AUX_COMP_SECURE_EN == 1)
547 NVIC_ClearTargetState(Aux_Comp_IRQn);
548#else
549 NVIC_SetTargetState(Aux_Comp_IRQn);
550#endif
551
552 //Attribuite 1
553#if (QSPI0_SECURE_EN == 1)
554 NVIC_ClearTargetState(Qspi0_IRQn);
555#else
556 NVIC_SetTargetState(Qspi0_IRQn);
557#endif
558
559#if (QSPI1_SECURE_EN == 1)
560 NVIC_ClearTargetState(Qspi1_IRQn);
561#else
562 NVIC_SetTargetState(Qspi1_IRQn);
563#endif
564
565#if (IRM_SECURE_EN == 1)
566 NVIC_ClearTargetState(Irm_IRQn);
567#else
568 NVIC_SetTargetState(Irm_IRQn);
569#endif
570
571#if (UART2_SECURE_EN == 1)
572 NVIC_ClearTargetState(Uart2_IRQn);
573#else
574 NVIC_SetTargetState(Uart2_IRQn);
575#endif
576
577#if (PWM_SECURE_EN == 1)
578 NVIC_ClearTargetState(Pwm0_IRQn);
579 NVIC_ClearTargetState(Pwm1_IRQn);
580 NVIC_ClearTargetState(Pwm2_IRQn);
581 NVIC_ClearTargetState(Pwm3_IRQn);
582 NVIC_ClearTargetState(Pwm4_IRQn);
583#else
584 NVIC_SetTargetState(Pwm0_IRQn);
585 NVIC_SetTargetState(Pwm1_IRQn);
586 NVIC_SetTargetState(Pwm2_IRQn);
587 NVIC_SetTargetState(Pwm3_IRQn);
588 NVIC_SetTargetState(Pwm4_IRQn);
589#endif
590
591#if (DMA0_SECURE_EN == 1)
592 NVIC_ClearTargetState(Dma_Ch0_IRQn);
593#else
594 NVIC_SetTargetState(Dma_Ch0_IRQn);
595#endif
596
597#if (DMA1_SECURE_EN == 1)
598 NVIC_ClearTargetState(Dma_Ch1_IRQn);
599#else
600 NVIC_SetTargetState(Dma_Ch1_IRQn);
601#endif
602
603#if (I2C_MASTER0_SECURE_EN == 1)
604 NVIC_ClearTargetState(I2C_Master0_IRQn);
605#else
606 NVIC_SetTargetState(I2C_Master0_IRQn);
607#endif
608
609#if (I2C_MASTER1_SECURE_EN == 1)
610 NVIC_ClearTargetState(I2C_Master1_IRQn);
611#else
612 NVIC_SetTargetState(I2C_Master1_IRQn);
613#endif
614
615#if (I2S0_SECURE_EN == 1)
616 NVIC_ClearTargetState(I2s0_IRQn);
617#else
618 NVIC_SetTargetState(I2s0_IRQn);
619#endif
620
621#if (SADC_SECURE_EN == 1)
622 NVIC_ClearTargetState(Sadc_IRQn);
623#else
624 NVIC_SetTargetState(Sadc_IRQn);
625#endif
626
627#if (SW_IRQ0_SECURE_EN == 1)
628 NVIC_ClearTargetState(Soft0_IRQn);
629#else
630 NVIC_SetTargetState(Soft0_IRQn);
631#endif
632
633#if (SW_IRQ1_SECURE_EN == 1)
634 NVIC_ClearTargetState(Soft1_IRQn);
635#else
636 NVIC_SetTargetState(Soft1_IRQn);
637#endif
638
639
640 //Attribuite 2
641#if (CRYPTO_SECURE_EN == 1)
642 NVIC_ClearTargetState(Crypto_IRQn);
643#else
644 NVIC_SetTargetState(Crypto_IRQn);
645#endif
646
647#if (PUF_OTP_SECURE_EN == 1)
648 NVIC_ClearTargetState(OTP_IRQn);
649#else
650 NVIC_SetTargetState(OTP_IRQn);
651#endif
652
653
654
655 //Nvic SetTargeStat function config interrupt to non sec wrold
656
657
658 /*Enable IDAU*/
659 SEC_CTRL->SEC_IDAU_CTRL = 1;
660
661 /*
662 * 2022/12/21: set SAU to be all non-secure
663 *
664 */
665 SAU->CTRL |= (SAU_CTRL_ALLNS_Msk);
666 /*NOTE: depends on system setting.*/
667
668}
669
670#endif
TZ_SAU_Setup
__STATIC_INLINE void TZ_SAU_Setup(void)
Definition partition.h:161
FPU_FPCCR_TS_VAL
#define FPU_FPCCR_TS_VAL
Definition partition.h:74
FPU_FPCCR_CLRONRETS_VAL
#define FPU_FPCCR_CLRONRETS_VAL
Definition partition.h:82
SCB_CSR_DEEPSLEEPS_VAL
#define SCB_CSR_DEEPSLEEPS_VAL
Definition partition.h:25
SCB_NSACR_CP10_11_VAL
#define SCB_NSACR_CP10_11_VAL
Definition partition.h:66
SCB_AIRCR_SYSRESETREQS_VAL
#define SCB_AIRCR_SYSRESETREQS_VAL
Definition partition.h:33
FPU_FPCCR_CLRONRET_VAL
#define FPU_FPCCR_CLRONRET_VAL
Definition partition.h:90
SCB_AIRCR_BFHFNMINS_VAL
#define SCB_AIRCR_BFHFNMINS_VAL
Definition partition.h:49
SCB_AIRCR_PRIS_VAL
#define SCB_AIRCR_PRIS_VAL
Definition partition.h:41