T32CM11_i2c.h File Reference

This is the chip specific include file for T32CM11 I2C Driver. note that there is a common include file for this HAL module that contains the APIs (such as the init function) that should be used by the application. More...

#include "tr_hal_platform.h"
#include "tr_hal_gpio.h"

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Data Structures
struct	I2C_REGISTERS_T
struct	tr_hal_i2c_settings_t
struct	tr_hal_i2c_int_count_t

Macros
#define	TR_HAL_MAX_I2C_CONTROLLER_ID   0
#define	NUM_I2C_CONTROLLER   1
#define	I2C_SCL_PIN_OPTION1   20
#define	I2C_SDA_PIN_OPTION1   21
#define	I2C_SCL_PIN_OPTION2   22
#define	I2C_SDA_PIN_OPTION2   23
#define	DEFAULT_I2C_SCL_PIN   I2C_SCL_PIN_OPTION2
#define	DEFAULT_I2C_SDA_PIN   I2C_SDA_PIN_OPTION2
#define	I2C_COMMAND_FIFO   32
#define	I2C_RX_FIFO_BYTES   16
#define	CHIP_MEMORY_MAP_I2C_CONTROLLER_BASE   0xA0100000
#define	I2C_STATUS_COMMAND_FIFO_EMPTY   0x01
#define	I2C_STATUS_READ_DATA_FIFO_NOT_EMPTY   0x02
#define	I2C_STATUS_ERROR_NO_ACK   0x04
#define	I2C_STATUS_ERROR_LOST_ARBITRATION   0x08
#define	I2C_STATUS_ERROR_READ_DATA_UNDERFLOW   0x10
#define	I2C_STATUS_COMMAND_FIFO_OVERFLOW   0x20
#define	I2C_STATUS_COMMAND_FIFO_FULL   0x40
#define	I2C_STATUS_TRANSFER_IN_PROGRESS   0x80
#define	I2C_STATUS_READ_DATA_FIFO_OVERFLOW   0x100
#define	I2C_STATUS_COMMAND_FIFO_UNDERFLOW   0x200
#define	I2C_STATUS_CLEAR_FIFO   0x400
#define	I2C_COMMAND_NULL   0x00
#define	I2C_COMMAND_WRITE_DATA_0   0x10
#define	I2C_COMMAND_WRITE_DATA_1   0x11
#define	I2C_COMMAND_WRITE_DATA_8   0x12
#define	I2C_COMMAND_READ_DATA_8   0x13
#define	I2C_COMMAND_STOP   0x14
#define	I2C_COMMAND_START   0x15
#define	I2C_COMMAND_VACK   0x16
#define	I2C_WRITE_DATA_BIT   0x00
#define	I2C_READ_DATA_BIT   0x01
#define	I2C_INTERRUPT_COMMAND_FIFO_EMPTY   0x01
#define	I2C_INTERRUPT_READ_DATA_FIFO_NOT_EMPTY   0x02
#define	I2C_INTERRUPT_ERROR   0x04
#define	I2C_INTERRUPT_LOSS_OF_ARBITRATION   0x08
#define	I2C_INTERRUPT_COMMAND_FIFO_DONE   0x10
#define	I2C_INTERRUPT_ALL   0x1F
#define	I2C_CONTROL_REG_I2C_ENABLE   0x80
#define	I2C_CONTROL_REG_I2C_DISABLE   0x00
#define	I2C_CONTROL_REG_CLOCK_SOURCE_APB   0x40
#define	I2C_CONTROL_REG_CLOCK_SOURCE_EXT   0x00
#define	I2C_CONTROL_REG_CLOCK_DIV_MASK   0x3F
#define	CLOCK_LOWER_SIX_BITS   0x2F
#define	I2C_CHIP_REGISTERS   ((I2C_REGISTERS_T *) CHIP_MEMORY_MAP_I2C_CONTROLLER_BASE)
#define	I2C_EVENT_TX_EMPTY   0x01
#define	I2C_EVENT_RX_FINISH   0x02
#define	I2C_EVENT_ERROR   0x04
#define	I2C_EVENT_ABORT_LOST_ARB   0x08
#define	I2C_EVENT_COMMAND_DONE   0x10
#define	I2C_CONFIG_CONTROLLER0

Typedefs
typedef void(*	tr_hal_i2c_receive_callback_t) (uint8_t received_byte)
typedef void(*	tr_hal_i2c_event_callback_t) (tr_hal_i2c_id_t i2c_id, uint32_t event_bitmask)

Enumerations
enum	tr_hal_i2c_id_t { I2C_CTRL_0_ID = 0 }
	On the T32CM11 there is just 1 I2C available to act as a Controller. More...
enum	tr_hal_i2c_clock_rate_t {   I2C_CLOCK_1_MHZ = 7 ,   I2C_CLOCK_800_KHZ = 9 ,   I2C_CLOCK_400_KHZ = 19 ,   I2C_CLOCK_200_KHZ = 39 ,   I2C_CLOCK_100_KHZ = 79 }

Functions
I2C_REGISTERS_T *	tr_hal_i2c_get_controller_register_address (tr_hal_i2c_id_t i2c_id)

Detailed Description

This is the chip specific include file for T32CM11 I2C Driver. note that there is a common include file for this HAL module that contains the APIs (such as the init function) that should be used by the application.

---

Trident HAL I2C Controller Driver:

I2C (Inter-Integrated Circuit) also known as IIC, is a 2-wire synchronous, multi-device serial communication protocol. it is simple and low cost but not the fastest (2 wires).

the 2 wires for I2C are: SDA == serial data SCL == serial clock

NXP (who created I2C as Philips in 1982 have changed the terminology of I2C and now substitude "Controller" for "Master" and "Target" for "Slave".

the CM11 chip has 1 I2C Controllers.

SPDX-License-Identifier: LicenseRef-TridentMSLA SPDX-FileCopyrightText: 2025 Trident IoT, LLC https://www.tridentiot.com

---

Macro Definition Documentation

CHIP_MEMORY_MAP_I2C_CONTROLLER_BASE

#define CHIP_MEMORY_MAP_I2C_CONTROLLER_BASE   0xA0100000

---

section 3.1 of the data sheet explains the Memory map this gives the base address for how to write the I2C registers the chip registers are how the software interacts with the I2C chip peripheral. We create a struct below that addresses the individual registers. This makes it so we can use this base address and a struct field to read or write a chip register

---

CLOCK_LOWER_SIX_BITS

#define CLOCK_LOWER_SIX_BITS   0x2F

DEFAULT_I2C_SCL_PIN

#define DEFAULT_I2C_SCL_PIN   I2C_SCL_PIN_OPTION2

DEFAULT_I2C_SDA_PIN

#define DEFAULT_I2C_SDA_PIN   I2C_SDA_PIN_OPTION2

I2C_CHIP_REGISTERS

#define I2C_CHIP_REGISTERS   ((I2C_REGISTERS_T *) CHIP_MEMORY_MAP_I2C_CONTROLLER_BASE)

I2C_COMMAND_FIFO

#define I2C_COMMAND_FIFO   32

I2C_COMMAND_NULL

#define I2C_COMMAND_NULL   0x00

I2C_COMMAND_READ_DATA_8

#define I2C_COMMAND_READ_DATA_8   0x13

I2C_COMMAND_START

#define I2C_COMMAND_START   0x15

I2C_COMMAND_STOP

#define I2C_COMMAND_STOP   0x14

I2C_COMMAND_VACK

#define I2C_COMMAND_VACK   0x16

I2C_COMMAND_WRITE_DATA_0

#define I2C_COMMAND_WRITE_DATA_0   0x10

I2C_COMMAND_WRITE_DATA_1

#define I2C_COMMAND_WRITE_DATA_1   0x11

I2C_COMMAND_WRITE_DATA_8

#define I2C_COMMAND_WRITE_DATA_8   0x12

I2C_CONFIG_CONTROLLER0

#define I2C_CONFIG_CONTROLLER0

Value:

    {                                                           \
        .sda_pin = (tr_hal_gpio_pin_t) { DEFAULT_I2C_SDA_PIN }, \
        .scl_pin = (tr_hal_gpio_pin_t) { DEFAULT_I2C_SCL_PIN }, \
        .clock_setting = I2C_CLOCK_100_KHZ,                     \
        .rx_handler_function = NULL,                            \
        .event_handler_fx = NULL,                               \
        .enable_chip_interrupts = true,                         \
        .interrupt_priority = TR_HAL_INTERRUPT_PRIORITY_5,      \
        .wake_on_interrupt = false,                             \
    }

---

initializer macros for default I2C CONTROLLER setting

---

I2C_CONTROL_REG_CLOCK_DIV_MASK

#define I2C_CONTROL_REG_CLOCK_DIV_MASK   0x3F

I2C_CONTROL_REG_CLOCK_SOURCE_APB

#define I2C_CONTROL_REG_CLOCK_SOURCE_APB   0x40

I2C_CONTROL_REG_CLOCK_SOURCE_EXT

#define I2C_CONTROL_REG_CLOCK_SOURCE_EXT   0x00

I2C_CONTROL_REG_I2C_DISABLE

#define I2C_CONTROL_REG_I2C_DISABLE   0x00

I2C_CONTROL_REG_I2C_ENABLE

#define I2C_CONTROL_REG_I2C_ENABLE   0x80

I2C_EVENT_ABORT_LOST_ARB

#define I2C_EVENT_ABORT_LOST_ARB   0x08

I2C_EVENT_COMMAND_DONE

#define I2C_EVENT_COMMAND_DONE   0x10

I2C_EVENT_ERROR

#define I2C_EVENT_ERROR   0x04

I2C_EVENT_RX_FINISH

#define I2C_EVENT_RX_FINISH   0x02

I2C_EVENT_TX_EMPTY

#define I2C_EVENT_TX_EMPTY   0x01

---

I2C events

---

I2C_INTERRUPT_ALL

#define I2C_INTERRUPT_ALL   0x1F

I2C_INTERRUPT_COMMAND_FIFO_DONE

#define I2C_INTERRUPT_COMMAND_FIFO_DONE   0x10

I2C_INTERRUPT_COMMAND_FIFO_EMPTY

#define I2C_INTERRUPT_COMMAND_FIFO_EMPTY   0x01

I2C_INTERRUPT_ERROR

#define I2C_INTERRUPT_ERROR   0x04

I2C_INTERRUPT_LOSS_OF_ARBITRATION

#define I2C_INTERRUPT_LOSS_OF_ARBITRATION   0x08

I2C_INTERRUPT_READ_DATA_FIFO_NOT_EMPTY

#define I2C_INTERRUPT_READ_DATA_FIFO_NOT_EMPTY   0x02

I2C_READ_DATA_BIT

#define I2C_READ_DATA_BIT   0x01

I2C_RX_FIFO_BYTES

#define I2C_RX_FIFO_BYTES   16

I2C_SCL_PIN_OPTION1

#define I2C_SCL_PIN_OPTION1   20

I2C_SCL_PIN_OPTION2

#define I2C_SCL_PIN_OPTION2   22

I2C_SDA_PIN_OPTION1

#define I2C_SDA_PIN_OPTION1   21

I2C_SDA_PIN_OPTION2

#define I2C_SDA_PIN_OPTION2   23

I2C_STATUS_CLEAR_FIFO

#define I2C_STATUS_CLEAR_FIFO   0x400

I2C_STATUS_COMMAND_FIFO_EMPTY

#define I2C_STATUS_COMMAND_FIFO_EMPTY   0x01

I2C_STATUS_COMMAND_FIFO_FULL

#define I2C_STATUS_COMMAND_FIFO_FULL   0x40

I2C_STATUS_COMMAND_FIFO_OVERFLOW

#define I2C_STATUS_COMMAND_FIFO_OVERFLOW   0x20

I2C_STATUS_COMMAND_FIFO_UNDERFLOW

#define I2C_STATUS_COMMAND_FIFO_UNDERFLOW   0x200

I2C_STATUS_ERROR_LOST_ARBITRATION

#define I2C_STATUS_ERROR_LOST_ARBITRATION   0x08

I2C_STATUS_ERROR_NO_ACK

#define I2C_STATUS_ERROR_NO_ACK   0x04

I2C_STATUS_ERROR_READ_DATA_UNDERFLOW

#define I2C_STATUS_ERROR_READ_DATA_UNDERFLOW   0x10

I2C_STATUS_READ_DATA_FIFO_NOT_EMPTY

#define I2C_STATUS_READ_DATA_FIFO_NOT_EMPTY   0x02

I2C_STATUS_READ_DATA_FIFO_OVERFLOW

#define I2C_STATUS_READ_DATA_FIFO_OVERFLOW   0x100

I2C_STATUS_TRANSFER_IN_PROGRESS

#define I2C_STATUS_TRANSFER_IN_PROGRESS   0x80

I2C_WRITE_DATA_BIT

#define I2C_WRITE_DATA_BIT   0x00

NUM_I2C_CONTROLLER

#define NUM_I2C_CONTROLLER   1

TR_HAL_MAX_I2C_CONTROLLER_ID

#define TR_HAL_MAX_I2C_CONTROLLER_ID   0

Typedef Documentation

tr_hal_i2c_event_callback_t

typedef void(* tr_hal_i2c_event_callback_t) (tr_hal_i2c_id_t i2c_id, uint32_t event_bitmask)

tr_hal_i2c_receive_callback_t

typedef void(* tr_hal_i2c_receive_callback_t) (uint8_t received_byte)

Enumeration Type Documentation

tr_hal_i2c_clock_rate_t

enum tr_hal_i2c_clock_rate_t

Enumerator
I2C_CLOCK_1_MHZ
I2C_CLOCK_800_KHZ
I2C_CLOCK_400_KHZ
I2C_CLOCK_200_KHZ
I2C_CLOCK_100_KHZ

tr_hal_i2c_id_t

enum tr_hal_i2c_id_t

On the T32CM11 there is just 1 I2C available to act as a Controller.

Enumerator
I2C_CTRL_0_ID

Function Documentation

tr_hal_i2c_get_controller_register_address()

I2C_REGISTERS_T * tr_hal_i2c_get_controller_register_address

(

tr_hal_i2c_id_t

i2c_id

)

---

if the app wants to directly interface with the chip registers, this is a convenience function for getting the address/struct of a particular I2C Controller so the chip registers can be accessed.

---