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T32CZ20_adc.h File Reference

This is the chip specific include file for T32CZ20 ADC Driver note that there is a common include file for this HAL module that contains the APIs (such as the init function) that should be used by the application. More...

#include "tr_hal_platform.h"
Include dependency graph for T32CZ20_adc.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct  CHAN_SETTINGS_T
union  tr_sadc_ana_set0_s
struct  tr_sadc_ana_set0_s::tr_sadc_ana_set0_b
union  tr_sadc_ana_set1_s
struct  tr_sadc_ana_set1_s::tr_sadc_ana_set1_b
struct  ADC_REGISTERS_T
 the struct we use so we can address registers using field names More...
union  tr_aux_comp_ana_ctl_s
struct  tr_aux_comp_ana_ctl_s::tr_aux_comp_ana_ctl_b
struct  AUX_COMPARATOR_REGISTERS_T
struct  tr_hal_adc_settings_t

Macros

#define TR_HAL_NUM_ADC   7
#define MAX_ADC_CHANNEL_ID   ADC_CHANNEL_6_ID
#define TR_HAL_ADC_CHANNEL_NONE   0xFF
#define TR_HAL_ADC_AIO0   21
#define TR_HAL_ADC_AIO1   22
#define TR_HAL_ADC_AIO2   23
#define TR_HAL_ADC_AIO4   28
#define TR_HAL_ADC_AIO5   29
#define TR_HAL_ADC_AIO6   30
#define TR_HAL_ADC_AIO7   31
#define ADC_VALID_PIN_CHOICE1   TR_HAL_ADC_AIO0
#define ADC_VALID_PIN_CHOICE2   TR_HAL_ADC_AIO1
#define ADC_VALID_PIN_CHOICE3   TR_HAL_ADC_AIO2
#define ADC_VALID_PIN_CHOICE4   TR_HAL_ADC_AIO4
#define ADC_VALID_PIN_CHOICE5   TR_HAL_ADC_AIO5
#define ADC_VALID_PIN_CHOICE6   TR_HAL_ADC_AIO6
#define ADC_VALID_PIN_CHOICE7   TR_HAL_ADC_AIO7
#define DEFAULT_ADC_PIN   ADC_VALID_PIN_CHOICE1
#define TR_ADC_ENABLE_AIO0   0x01UL
#define TR_ADC_ENABLE_AIO1   0x02UL
#define TR_ADC_ENABLE_AIO2   0x04UL
#define TR_ADC_ENABLE_AIO4   0x10UL
#define TR_ADC_ENABLE_AIO5   0x20UL
#define TR_ADC_ENABLE_AIO6   0x40UL
#define TR_ADC_ENABLE_AIO7   0x80UL
#define CHIP_MEMORY_MAP_ADC_BASE   (0x4002F000UL)
#define CHIP_MEMORY_MAP_AUX_COMPARATOR_BASE   (0x4001E000UL)
#define ADC_REG_ENABLE_ADC_DISABLE   0x000
#define ADC_REG_ENABLE_ADC_ENABLE   0x001
#define ADC_REG_ENABLE_VGA_ENABLE   0x02
#define ADC_REG_ENABLE_LDO_ENABLE   0x04
#define ADC_REG_ENABLE_CLK_FREE   0x100
#define ADC_REG_RESET_ADC   0x001
#define ADC_REG_RESET_FIFO   0x100
#define ADC_REG_START_ADC   0x01
#define ADC_REG_TIMER_RATE_DEPENDS_ON_SOFTWARE   0x00
#define ADC_REG_TIMER_RATE_DEPENDS_ON_TIMER   0x01
#define ADC_REG_TIMER_USE_SYSTEM_CLOCK   0x00
#define ADC_REG_TIMER_USE_SLOW_CLOCK   0x02
#define ADC_REG_TIMER_RISING_EDGE   0x00
#define ADC_REG_TIMER_FALLING_EDGE   0x04
#define ADC_REG_TIMER_DEBUG_MASK   0x78
#define ADC_REG_TIMER_CLOCK_DIV_MASK   0xFFFF0000
#define ADC_REG_TIMER_CLOCK_DIV_SHIFT   16
#define TR_HAL_ADC_MAX_CLOCK_DIVISOR   65536
#define TR_HAL_ADC_MIN_CLOCK_DIVISOR   3
#define ADC_REG_SAMPLE_OUTPUT_RESOLUTION_8_BIT   0x00
#define ADC_REG_SAMPLE_OUTPUT_RESOLUTION_10_BIT   0x01
#define ADC_REG_SAMPLE_OUTPUT_RESOLUTION_12_BIT   0x02
#define ADC_REG_SAMPLE_OUTPUT_RESOLUTION_14_BIT   0x03
#define ADC_REG_SAMPLE_SELECT_CHANNEL_0   0x00
#define ADC_REG_SAMPLE_SELECT_CHANNEL_1   0x10
#define ADC_REG_SAMPLE_SELECT_CHANNEL_2   0x20
#define ADC_REG_SAMPLE_SELECT_CHANNEL_3   0x30
#define ADC_REG_SAMPLE_SELECT_CHANNEL_4   0x40
#define ADC_REG_SAMPLE_SELECT_CHANNEL_5   0x50
#define ADC_REG_SAMPLE_SELECT_CHANNEL_6   0x60
#define ADC_REG_SAMPLE_SELECT_CHANNEL_7   0x70
#define ADC_REG_SAMPLE_SELECT_CHANNEL_8   0x80
#define ADC_REG_SAMPLE_SELECT_CHANNEL_9   0x90
#define ADC_REG_SAMPLE_VALUE_BYPASS   0x1000
#define ADC_REG_SAMPLE_MSB_BIT_INVERSION   0x2000
#define ADC_REG_SAMPLE_ENABLE_MANUAL_MODE1   0x4000
#define ADC_REG_SAMPLE_ENABLE_MANUAL_MODE2   0x8000
#define ADC_REG_SAMPLE_CALIBRATION_MASK   0x0FFF0000
#define ADC_CONFIG_REG_P_CHANNEL_AIN_0   0x00000000
#define ADC_CONFIG_REG_P_CHANNEL_AIN_1   0x00000001
#define ADC_CONFIG_REG_P_CHANNEL_AIN_2   0x00000002
#define ADC_CONFIG_REG_P_CHANNEL_AIN_3   0x00000003
#define ADC_CONFIG_REG_P_CHANNEL_AIN_4   0x00000004
#define ADC_CONFIG_REG_P_CHANNEL_AIN_5   0x00000005
#define ADC_CONFIG_REG_P_CHANNEL_AIN_6   0x00000006
#define ADC_CONFIG_REG_P_CHANNEL_AIN_7   0x00000007
#define ADC_CONFIG_REG_P_CHANNEL_TEMP_SENSOR   0x00000008
#define ADC_CONFIG_REG_P_CHANNEL_BATT_VOLT   0x0000000A
#define ADC_CONFIG_REG_P_CHANNEL_NONE   0x0000000F
#define ADC_CONFIG_REG_N_CHANNEL_AIN_0   0x00000000
#define ADC_CONFIG_REG_N_CHANNEL_AIN_1   0x00000010
#define ADC_CONFIG_REG_N_CHANNEL_AIN_2   0x00000020
#define ADC_CONFIG_REG_N_CHANNEL_AIN_3   0x00000030
#define ADC_CONFIG_REG_N_CHANNEL_AIN_4   0x00000040
#define ADC_CONFIG_REG_N_CHANNEL_AIN_5   0x00000050
#define ADC_CONFIG_REG_N_CHANNEL_AIN_6   0x00000060
#define ADC_CONFIG_REG_N_CHANNEL_AIN_7   0x00000070
#define ADC_CONFIG_REG_N_CHANNEL_TEMP_SENSOR   0x00000080
#define ADC_CONFIG_REG_N_CHANNEL_BATT_VOLT   0x000000A0
#define ADC_CONFIG_REG_N_CHANNEL_NONE   0x000000F0
#define ADC_CONFIG_REG_MAX_GAIN_SETTING   63
#define ADC_CONFIG_REG_DEFAULT_GAIN   0x00001400
#define ADC_CONFIG_REG_SELECT_REF_IN   0x00004000
#define ADC_CONFIG_REG_P_CHAN_PULL_NONE   0x00000000
#define ADC_CONFIG_REG_N_CHAN_PULL_NONE   0x00000000
#define ADC_CONFIG_REG_P_CHAN_PULL_HIGH   0x00010000
#define ADC_CONFIG_REG_P_CHAN_PULL_LOW   0x00020000
#define ADC_CONFIG_REG_N_CHAN_PULL_HIGH   0x00040000
#define ADC_CONFIG_REG_N_CHAN_PULL_LOW   0x00080000
#define ADC_CONFIG_REG_P_CHAN_TO_VDD   0x00100000
#define ADC_CONFIG_REG_P_CHAN_TO_GND   0x00200000
#define ADC_CONFIG_REG_N_CHAN_TO_VDD   0x00400000
#define ADC_CONFIG_REG_N_CHAN_TO_GND   0x00800000
#define ADC_CONFIG_REG_P_CHAN_VCM_VOLTAGE   0x00030000
#define ADC_CONFIG_REG_N_CHAN_VCM_VOLTAGE   0x000C0000
#define ADC_CONFIG_REG_PULL_NONE   0x00000000
#define ADC_CONFIG_REG_PULL_VCM_MODE   0x000F0000
#define ADC_CONFIG_REG_AQUISITION_TIME_0p3_uS   0x00000000
#define ADC_CONFIG_REG_AQUISITION_TIME_1_uS   0x01000000
#define ADC_CONFIG_REG_AQUISITION_TIME_2_uS   0x02000000
#define ADC_CONFIG_REG_AQUISITION_TIME_3_uS   0x03000000
#define ADC_CONFIG_REG_AQUISITION_TIME_4_uS   0x04000000
#define ADC_CONFIG_REG_AQUISITION_TIME_8_uS   0x05000000
#define ADC_CONFIG_REG_AQUISITION_TIME_12_uS   0x06000000
#define ADC_CONFIG_REG_AQUISITION_TIME_16_uS   0x07000000
#define ADC_CONFIG_REG_END_DELAY_TIME_0p3_uS   0x00000000
#define ADC_CONFIG_REG_END_DELAY_TIME_1_uS   0x10000000
#define ADC_CONFIG_REG_END_DELAY_TIME_2_uS   0x20000000
#define ADC_CONFIG_REG_END_DELAY_TIME_3_uS   0x30000000
#define ADC_CONFIG_REG_END_DELAY_TIME_4_uS   0x40000000
#define ADC_CONFIG_REG_END_DELAY_TIME_8_uS   0x50000000
#define ADC_CONFIG_REG_END_DELAY_TIME_12_uS   0x60000000
#define ADC_CONFIG_REG_END_DELAY_TIME_16_uS   0x70000000
#define ADC_CONFIG_REG_CLEAR_VALUE   0x240000FF
#define ADC_BURST_REG_DISABLE_BURST   0x00000000
#define ADC_BURST_REG_ENABLE_BURST   0x80000000
#define ADC_THRESHHOLD_LOW_DEFAULT   0x00000000
#define ADC_THRESHHOLD_HIGH_DEFAULT   0x3FFF0000
#define ADC_ENDMA_REG_ENABLE_DMA   0x01
#define ADC_ENDMA_REG_RESET_DMA   0x01
#define ADC_DMASET_REG_LOAD_ADDR_ON_DMA_START   0x00
#define ADC_DMASET_REG_LOAD_ADDR_ON_DMA_RESET   0x01
#define ADC_DMASET_REG_4_BYTE_FORMAT   0x00
#define ADC_DMASET_REG_2_BYTE_FORMAT   0x10
#define ADC_DMASET_REG_1_BYTE_FORMAT   0x20
#define TR_HAL_ADC_INTERRUPT_DMA   0x0000001
#define TR_HAL_ADC_INTERRUPT_DONE   0x0000004
#define TR_HAL_ADC_INTERRUPT_VALID   0x0000008
#define TR_HAL_ADC_INTERRUPT_MODE_DONE   0x0000010
#define TR_HAL_ADC_INTERRUPT_CHAN_0   0x0040000
#define TR_HAL_ADC_INTERRUPT_CHAN_1   0x0080000
#define TR_HAL_ADC_INTERRUPT_CHAN_2   0x0100000
#define TR_HAL_ADC_INTERRUPT_CHAN_3   0x0200000
#define TR_HAL_ADC_INTERRUPT_CHAN_4   0x0400000
#define TR_HAL_ADC_INTERRUPT_CHAN_5   0x0800000
#define TR_HAL_ADC_INTERRUPT_CHAN_6   0x1000000
#define TR_HAL_ADC_INTERRUPT_CHAN_7   0x2000000
#define TR_HAL_ADC_INTERRUPT_LOW_THRESH   0x0003FF00
#define TR_HAL_ADC_INTERRUPT_HIGH_THRESH   0x0FFC0000
#define TR_HAL_ADC_INTERRUPT_ALL   0x0FFFFF1D
#define TR_HAL_ADC_INTERRUPT_BASE   0x0000001D
#define TR_HAL_ADC_EVENT_CH_0_RESULT   0x001
#define TR_HAL_ADC_EVENT_CH_1_RESULT   0x002
#define TR_HAL_ADC_EVENT_CH_2_RESULT   0x004
#define TR_HAL_ADC_EVENT_CH_3_RESULT   0x008
#define TR_HAL_ADC_EVENT_CH_4_RESULT   0x010
#define TR_HAL_ADC_EVENT_CH_5_RESULT   0x020
#define TR_HAL_ADC_EVENT_CH_6_RESULT   0x040
#define TR_HAL_ADC_EVENT_CH_7_RESULT   0x080
#define TR_HAL_ADC_EVENT_ALL_CH_DONE   0x100
#define TR_HAL_ADC_EVENT_DMA   0x200
#define TR_HAL_ADC_R0_RESULT_MASK   0x00003FFF
#define TR_HAL_ADC_R1_RESULT_MASK   0x00000FFF
#define TR_HAL_ADC_R2_RESULT_MASK   0x00000FFF
#define ADC_REGISTERS   ((ADC_REGISTERS_T *) CHIP_MEMORY_MAP_ADC_BASE)
#define AUX_COMP_REGISTERS   ((AUX_COMPARATOR_REGISTERS_T *) CHIP_MEMORY_MAP_AUX_COMPARATOR_BASE)
#define TR_HAL_ADC_DEFAULT_GAIN   6
#define TR_HAL_ADC_THRESH_LOW_DEFAULT   0x0000
#define TR_HAL_ADC_THRESH_HIGH_DEFAULT   0x0003
#define DEFAULT_ADC_SINGLE_ENDED_CONFIG

Typedefs

typedef union tr_sadc_ana_set0_s tr_sadc_ana_set0_t
typedef union tr_sadc_ana_set1_s tr_sadc_ana_set1_t
typedef union tr_aux_comp_ana_ctl_s tr_aux_comp_ana_ctl_t
typedef void(* tr_hal_adc_event_callback_t) (uint32_t raw_result, uint32_t converted_result, uint32_t event_bitmask, uint32_t int_status)

Enumerations

enum  tr_hal_adc_channel_id_t {
  ADC_CHANNEL_0_ID = 0 ,
  ADC_CHANNEL_1_ID = 1 ,
  ADC_CHANNEL_2_ID = 2 ,
  ADC_CHANNEL_3_ID = 3 ,
  ADC_CHANNEL_4_ID = 4 ,
  ADC_CHANNEL_5_ID = 5 ,
  ADC_CHANNEL_6_ID = 6
}
enum  tr_hal_adc_oversample_t {
  TR_HAL_ADC_REG_SAMPLE_NO_OVERSAMPLE = 0x000 ,
  TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_2 = 0x100 ,
  TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_4 = 0x200 ,
  TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_8 = 0x300 ,
  TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_16 = 0x400 ,
  TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_32 = 0x500 ,
  TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_64 = 0x600 ,
  TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_128 = 0x700 ,
  TR_HAL_ADC_REG_SAMPLE_OVERSAMPLE_256 = 0x800
}
enum  tr_hal_adc_mode_t {
  TR_HAL_ADC_MODE_ONE_SHOT = 0 ,
  TR_HAL_ADC_MODE_TIMER = 1 ,
  TR_HAL_ADC_MODE_SCAN = 2
}
enum  tr_hal_adc_resolution_t {
  TR_HAL_ADC_MODE_RESOLUTION_8_BIT = ADC_REG_SAMPLE_OUTPUT_RESOLUTION_8_BIT ,
  TR_HAL_ADC_MODE_RESOLUTION_10_BIT = ADC_REG_SAMPLE_OUTPUT_RESOLUTION_10_BIT ,
  TR_HAL_ADC_MODE_RESOLUTION_12_BIT = ADC_REG_SAMPLE_OUTPUT_RESOLUTION_12_BIT ,
  TR_HAL_ADC_MODE_RESOLUTION_14_BIT = ADC_REG_SAMPLE_OUTPUT_RESOLUTION_14_BIT
}
enum  tr_hal_adc_pull_mode_t {
  TR_HAL_ADC_PULL_LOW = 0 ,
  TR_HAL_ADC_PULL_HIGH = 1 ,
  TR_HAL_ADC_PULL_TO_VCC = 2 ,
  TR_HAL_ADC_PULL_TO_GND = 3 ,
  TR_HAL_ADC_PULL_NOT_USED = 4
}
enum  tr_hal_adc_clock_t {
  TR_HAL_ADC_USE_SYSTEM_CLOCK = 0 ,
  TR_HAL_ADC_USE_SLOW_CLOCK = 1
}
enum  tr_hal_time_t {
  TR_HAL_ADC_TIME_HALF = 0 ,
  TR_HAL_ADC_TIME_1 = 1 ,
  TR_HAL_ADC_TIME_2 = 2 ,
  TR_HAL_ADC_TIME_3 = 3 ,
  TR_HAL_ADC_TIME_4 = 4 ,
  TR_HAL_ADC_TIME_8 = 5 ,
  TR_HAL_ADC_TIME_12 = 6 ,
  TR_HAL_ADC_TIME_16 = 7
}

Detailed Description

This is the chip specific include file for T32CZ20 ADC Driver note that there is a common include file for this HAL module that contains the APIs (such as the init function) that should be used by the application.

SPDX-License-Identifier: LicenseRef-TridentMSLA SPDX-FileCopyrightText: 2025 Trident IoT, LLC https://www.tridentiot.com