Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

• random_number_select : SYS_CTRL_REGISTERS_T
• random_number_status : SYS_CTRL_REGISTERS_T
• random_number_trigger : SYS_CTRL_REGISTERS_T
• random_number_value : SYS_CTRL_REGISTERS_T
• raw_tx_buff_length : tr_hal_spi_settings_t, tr_hal_uart_settings_t
• raw_tx_buffer : tr_hal_spi_settings_t, tr_hal_uart_settings_t
• read_data : I2C_REGISTERS_T
• read_exit_on_crazy : tr_hal_i2c_int_count_t
• read_exit_on_flag : tr_hal_i2c_int_count_t
• read_exit_on_int_status : tr_hal_i2c_int_count_t
• receive_buffer_register : UART_REGISTERS_T
• receive_watermark : tr_hal_spi_settings_t
• reg : tr_aux_comp_ana_ctl_s, tr_sadc_ana_set0_s, tr_sadc_ana_set1_s
• reg_data_0_save : PWM_REGISTERS_T
• reg_data_1_save : PWM_REGISTERS_T
• repeat_delay : TIMER_REGISTERS_T
• reserved : SECURITY_CTRL_REGISTERS_T, SYS_CTRL_REGISTERS_T
• reserved0 : POWER_MGMT_REGISTERS_T
• RESERVED1 : rco32k_result0_, rco32k_result1_, tr_aux_comp_ana_ctl_s::tr_aux_comp_ana_ctl_b, tr_sadc_ana_set0_s::tr_sadc_ana_set0_b, tr_sadc_ana_set1_s::tr_sadc_ana_set1_b
• reserved1 : ADC_REGISTERS_T, GPIO_REGISTERS_T, POWER_MGMT_REGISTERS_T, PWM_REGISTERS_T, SPI_REGISTERS_T, TRNG_REGISTERS_T
• RESERVED2 : rco32k_result0_, rco32k_result1_, tr_aux_comp_ana_ctl_s::tr_aux_comp_ana_ctl_b, tr_sadc_ana_set0_s::tr_sadc_ana_set0_b, tr_sadc_ana_set1_s::tr_sadc_ana_set1_b
• reserved2 : ADC_REGISTERS_T, GPIO_REGISTERS_T, POWER_MGMT_REGISTERS_T, PWM_REGISTERS_T, SPI_REGISTERS_T, SYS_CTRL_REGISTERS_T, TRNG_REGISTERS_T
• RESERVED3 : rco32k_result0_, tr_sadc_ana_set0_s::tr_sadc_ana_set0_b, tr_sadc_ana_set1_s::tr_sadc_ana_set1_b
• reserved3 : ADC_REGISTERS_T, POWER_MGMT_REGISTERS_T, PWM_REGISTERS_T, SPI_REGISTERS_T, SYS_CTRL_REGISTERS_T, TRNG_REGISTERS_T
• RESERVED4 : tr_sadc_ana_set0_s::tr_sadc_ana_set0_b
• reserved4 : POWER_MGMT_REGISTERS_T, PWM_REGISTERS_T, SPI_REGISTERS_T
• reserved_1 : SPI_REGISTERS_T
• reserved_old_map : SYS_CTRL_REGISTERS_T
• reset : PWM_REGISTERS_T
• reset_counter : WDOG_REGISTERS_T
• reset_dma : ADC_REGISTERS_T
• reset_enabled : tr_hal_wdog_settings_t
• reset_reason : DEEP_POWER_DOWN_REGISTERS_T
• reset_watchdog : WDOG_REGISTERS_T
• resolution : tr_hal_adc_settings_t
• result_analog : ADC_REGISTERS_T
• result_digital : ADC_REGISTERS_T
• result_oversample : ADC_REGISTERS_T
• retention_0 : DEEP_POWER_DOWN_REGISTERS_T
• retention_1 : DEEP_POWER_DOWN_REGISTERS_T
• retention_2 : DEEP_POWER_DOWN_REGISTERS_T
• retention_3 : DEEP_POWER_DOWN_REGISTERS_T
• rseq_delay : PWM_REGISTERS_T
• rseq_num_elements : PWM_REGISTERS_T
• rseq_num_repeats : PWM_REGISTERS_T
• rtc_date_time : tr_hal_rtc_settings_t
• rts_pin : tr_hal_uart_settings_t
• run_as_controller : tr_hal_spi_settings_t
• run_when_sleeping : tr_hal_uart_settings_t
• rx_bytes_before_trigger : tr_hal_uart_settings_t
• rx_dma_buff_length : tr_hal_spi_settings_t, tr_hal_uart_settings_t
• rx_dma_buffer : tr_hal_spi_settings_t, tr_hal_uart_settings_t
• rx_dma_enabled : tr_hal_spi_settings_t, tr_hal_uart_settings_t
• rx_fifo_current_level : SPI_REGISTERS_T
• rx_handler_function : tr_hal_i2c_settings_t, tr_hal_spi_settings_t, tr_hal_uart_settings_t
• rx_pin : tr_hal_uart_settings_t