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Trident IoT SDK
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Trident IoT SDK
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Collaboration diagram for GPIO CZ20:Data Structures | |
| struct | GPIO_REGISTERS_T |
| struct | SYS_CTRL_REGISTERS_T |
| offsets for where to find chip registers needed for System Control register which is used to configure GPIO pins (what mode are they in and pull up/down and open drain enable, etc see section 19.3 in the chip datasheet More... | |
| struct | tr_hal_gpio_settings_t |
Typedefs | |
| typedef void(* | tr_hal_gpio_event_callback_t) (tr_hal_gpio_pin_t pin, tr_hal_gpio_event_t event) |
| #define CHIP_MEMORY_MAP_GPIO_BASE (0x40001000UL) |
chip register addresses section 2.2 of the data sheet explains the Memory map. this gives the base address for how to write the chip registers the chip registers are how the software interacts configures GPIOs, reads GPIOs, and gets/sets information on the chip We create a struct below that addresses the individual registers. This makes it so we can use this base address and a struct field to read or write a chip register
| #define CHIP_MEMORY_MAP_SYS_CTRL_BASE (0x40000000UL) |
| #define DEFAULT_GPIO_INPUT_CONFIG |
| #define DEFAULT_GPIO_OUTPUT_CONFIG |
default values so an app can quickly load a reasonable set of values for an input or output GPIO
| #define GPIO_CHIP_REGISTERS ((GPIO_REGISTERS_T *) CHIP_MEMORY_MAP_GPIO_BASE) |
| #define SCC_UART0_CLOCK_BIT 16 |
| #define SCC_UART1_CLOCK_BIT 17 |
| #define SCC_UART2_CLOCK_BIT 18 |
| #define set_output_high state |
| #define set_output_low interrupt_status |
| #define SYS_CTRL_BASEBAND_FREQ_36_MHZ 0x600 |
| #define SYS_CTRL_BASEBAND_FREQ_40_MHZ 0x700 |
| #define SYS_CTRL_BASEBAND_FREQ_48_MHZ 0x00 |
| #define SYS_CTRL_BASEBAND_FREQ_64_MHZ 0x100 |
| #define SYS_CTRL_BASEBAND_PLL_DISABLE 0x0000 |
| #define SYS_CTRL_BASEBAND_PLL_ENABLE 0x8000 |
| #define SYS_CTRL_CHIP_REGISTERS ((SYS_CTRL_REGISTERS_T *) CHIP_MEMORY_MAP_SYS_CTRL_BASE) |
| #define SYS_CTRL_HCLK_SELECT_MASK 0x03 |
| #define SYS_CTRL_HCLK_SELECT_PLL_CLK 0x01 |
| #define SYS_CTRL_HCLK_SELECT_RCO_1M 0x03 |
| #define SYS_CTRL_HCLK_SELECT_XTAL_CLK 0x00 |
| #define SYS_CTRL_HCLK_SELECT_XTAL_CLK_DIV2 0x02 |
| #define SYS_CTRL_PER_CLK_SELECT_MASK 0x0C |
| #define SYS_CTRL_PER_CLK_SELECT_RCO_1M 0x08 |
| #define SYS_CTRL_PER_CLK_SELECT_XTAL_CLK 0x00 |
| #define SYS_CTRL_PER_CLK_SELECT_XTAL_CLK_DIV2 0x04 |
| #define SYS_CTRL_PWM0_CLOCK_SELECT_BIT_SHIFT 16 |
| #define SYS_CTRL_PWM1_CLOCK_SELECT_BIT_SHIFT 18 |
| #define SYS_CTRL_PWM2_CLOCK_SELECT_BIT_SHIFT 20 |
| #define SYS_CTRL_PWM3_CLOCK_SELECT_BIT_SHIFT 22 |
| #define SYS_CTRL_PWM4_CLOCK_SELECT_BIT_SHIFT 24 |
| #define SYS_CTRL_PWM_CLOCK_SELECT_HCLK 0x00 |
| #define SYS_CTRL_PWM_CLOCK_SELECT_PER_CLK 0x01 |
| #define SYS_CTRL_PWM_CLOCK_SELECT_RCO_1M 0x02 |
| #define SYS_CTRL_PWM_CLOCK_SELECT_SLOW_CLK 0x03 |
| #define SYS_CTRL_SLOW_CLK_ENABLE_EXTERNAL 0x2000 |
| #define SYS_CTRL_SLOW_CLK_EXTERNAL_SRC_SHIFT 8 |
| #define SYS_CTRL_SLOW_CLK_SELECT_EXTERNAL 0xC0 |
| #define SYS_CTRL_SLOW_CLK_SELECT_MASK 0xC0 |
| #define SYS_CTRL_SLOW_CLK_SELECT_RCO_32K 0x00 |
| #define SYS_CTRL_SLOW_CLK_SELECT_XO_32K 0x40 |
| #define SYS_CTRL_TIMER0_CLOCK_SELECT_BIT_SHIFT 26 |
| #define SYS_CTRL_TIMER1_CLOCK_SELECT_BIT_SHIFT 28 |
| #define SYS_CTRL_TIMER2_CLOCK_SELECT_BIT_SHIFT 30 |
| #define SYS_CTRL_TIMER_CLOCK_SELECT_PER_CLK 0x00 |
| #define SYS_CTRL_TIMER_CLOCK_SELECT_RCO_1M 0x02 |
| #define SYS_CTRL_TIMER_CLOCK_SELECT_SLOW_CLK 0x03 |
| #define SYS_CTRL_UART0_CLOCK_SELECT_BIT_SHIFT 0 |
| #define SYS_CTRL_UART1_CLOCK_SELECT_BIT_SHIFT 2 |
| #define SYS_CTRL_UART2_CLOCK_SELECT_BIT_SHIFT 4 |
| #define SYS_CTRL_UART_CLOCK_SELECT_PER_CLOCK 0x00 |
| #define SYS_CTRL_UART_CLOCK_SELECT_RCO_1M 0x02 |
| #define SYS_CTRL_UART_CLOCK_SELECT_RCO_32K 0x03 |
| #define TR_HAL_MAX_PIN_NUMBER (32) |
max pin number
| #define TR_HAL_NUM_DRIVE_REGISTERS 2 |
| #define TR_HAL_NUM_PULL_REGISTERS 4 |
defines for dealing with the SYS_CTRL pull registers and drive registers
| #define TR_HAL_PINS_PER_DRIVE_REG 16 |
| #define TR_HAL_PINS_PER_PULL_REG 8 |
| #define TR_HAL_POWER_DEEP_SLEEP 0x02 |
| #define TR_HAL_POWER_LITE_SLEEP 0x01 |
| #define TR_HAL_POWER_NORMAL 0x00 |
| #define TR_HAL_POWER_POWERDOWN 0x04 |
| typedef void(* tr_hal_gpio_event_callback_t) (tr_hal_gpio_pin_t pin, tr_hal_gpio_event_t event) |
values for setting the debounce time register each individual GPIO can be set to enable or disable debounce but the debounce time is set globally for ALL GPIOs. NOTE: these CANNOT be changed. These come from the chip data sheet
| enum tr_hal_direction_t |
values for setting the GPIO drive strength in the Trident HAL APIs NOTE: these CANNOT be changed. These come from the chip data sheet
| Enumerator | |
|---|---|
| TR_HAL_DRIVE_STRENGTH_4_MA | |
| TR_HAL_DRIVE_STRENGTH_10_MA | |
| TR_HAL_DRIVE_STRENGTH_14_MA | |
| TR_HAL_DRIVE_STRENGTH_20_MA | |
| TR_HAL_DRIVE_STRENGTH_MAX | |
| TR_HAL_DRIVE_STRENGTH_DEFAULT | |
| enum tr_hal_gpio_event_t |
| enum tr_hal_level_t |
| enum tr_hal_pin_mode_t |
these are the pin MODEs to be passed to tr_hal_gpio_set_mode note that these are defined by the chip and cannot be changed see section 17.3 of datasheet
| enum tr_hal_pullopt_t |
values for setting the pull option in the Trident HAL GPIO APIs NOTE: these CANNOT be changed. These are in the chip data sheet THESE ARE NOT ARBITRARY
| enum tr_hal_trigger_t |
| enum tr_hal_wake_mode_t |
1.10.0