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Data Fields
SYS_CTRL_REGISTERS_T Struct Reference
Trident HAL » T32CM11 specific » GPIO CM11 | Trident HAL » T32CZ20 specific » GPIO CZ20

offsets for where to find chip registers needed for System Control register which is used to configure GPIO pins (what mode are they in and pull up/down and open drain enable, etc see section 19.3 in the chip datasheet More...

#include <T32CM11_gpio.h>

Data Fields

__IO uint32_t sleep_enable
 
__IO uint32_t system_clock_control
 
__IO uint32_t reserved [2]
 
__IO uint32_t gpio_pin_map [TR_HAL_NUM_MODE_REGISTERS]
 
__IO uint32_t gpio_pull_ctrl [TR_HAL_NUM_PULL_REGISTERS]
 
__IO uint32_t gpio_drv_ctrl [TR_HAL_NUM_DRIVE_REGISTERS]
 
__IO uint32_t open_drain_enable
 
__IO uint32_t analog_IO_enable
 
__IO uint32_t random_number_trigger
 
__IO uint32_t random_number_select
 
__IO uint32_t random_number_status
 
__IO uint32_t random_number_value
 
__IO uint32_t reserved2 [4]
 
__IO uint32_t scratchpad [8]
 
__IO uint32_t enable_wake_on_high
 
__IO uint32_t enable_wake_on_low
 
__IO uint32_t reserved3 [2]
 
__IO uint32_t chip_info
 
__IO uint32_t system_clock_control_0
 
__IO uint32_t system_clock_control_1
 
__IO uint32_t system_power_state
 
__IO uint32_t reserved_old_map [4]
 
__IO uint32_t enable_schmitt
 
__IO uint32_t enable_filter
 
__IO uint32_t aio_control
 
__IO uint32_t cache_control
 
__IO uint32_t pwm_select
 
__IO uint32_t sram_lowpower_0
 
__IO uint32_t sram_lowpower_1
 
__IO uint32_t sram_lowpower_2
 
__IO uint32_t sram_lowpower_3
 
__IO uint32_t system_clock_control_2
 
__IO uint32_t system_test
 
__IO uint32_t gpio_output_mux [8]
 
__IO uint32_t gpio_input_mux [8]
 

Detailed Description

offsets for where to find chip registers needed for System Control register which is used to configure GPIO pins (what mode are they in and pull up/down and open drain enable, etc see section 19.3 in the chip datasheet

offsets for where to find chip registers needed for System Control register which is used to configure GPIO pins (what mode are they in and pull up/down and open drain enable, etc see section 17.4.2 in the chip datasheet

Field Documentation

◆ aio_control

__IO uint32_t SYS_CTRL_REGISTERS_T::aio_control

◆ analog_IO_enable

__IO uint32_t SYS_CTRL_REGISTERS_T::analog_IO_enable

◆ cache_control

__IO uint32_t SYS_CTRL_REGISTERS_T::cache_control

◆ chip_info

__IO uint32_t SYS_CTRL_REGISTERS_T::chip_info

◆ enable_filter

__IO uint32_t SYS_CTRL_REGISTERS_T::enable_filter

◆ enable_schmitt

__IO uint32_t SYS_CTRL_REGISTERS_T::enable_schmitt

◆ enable_wake_on_high

__IO uint32_t SYS_CTRL_REGISTERS_T::enable_wake_on_high

◆ enable_wake_on_low

__IO uint32_t SYS_CTRL_REGISTERS_T::enable_wake_on_low

◆ gpio_drv_ctrl

__IO uint32_t SYS_CTRL_REGISTERS_T::gpio_drv_ctrl

◆ gpio_input_mux

__IO uint32_t SYS_CTRL_REGISTERS_T::gpio_input_mux[8]

◆ gpio_output_mux

__IO uint32_t SYS_CTRL_REGISTERS_T::gpio_output_mux[8]

◆ gpio_pin_map

__IO uint32_t SYS_CTRL_REGISTERS_T::gpio_pin_map[TR_HAL_NUM_MODE_REGISTERS]

◆ gpio_pull_ctrl

__IO uint32_t SYS_CTRL_REGISTERS_T::gpio_pull_ctrl

◆ open_drain_enable

__IO uint32_t SYS_CTRL_REGISTERS_T::open_drain_enable

◆ pwm_select

__IO uint32_t SYS_CTRL_REGISTERS_T::pwm_select

◆ random_number_select

__IO uint32_t SYS_CTRL_REGISTERS_T::random_number_select

◆ random_number_status

__IO uint32_t SYS_CTRL_REGISTERS_T::random_number_status

◆ random_number_trigger

__IO uint32_t SYS_CTRL_REGISTERS_T::random_number_trigger

◆ random_number_value

__IO uint32_t SYS_CTRL_REGISTERS_T::random_number_value

◆ reserved

__IO uint32_t SYS_CTRL_REGISTERS_T::reserved

◆ reserved2

__IO uint32_t SYS_CTRL_REGISTERS_T::reserved2[4]

◆ reserved3

__IO uint32_t SYS_CTRL_REGISTERS_T::reserved3[2]

◆ reserved_old_map

__IO uint32_t SYS_CTRL_REGISTERS_T::reserved_old_map[4]

◆ scratchpad

__IO uint32_t SYS_CTRL_REGISTERS_T::scratchpad[8]

◆ sleep_enable

__IO uint32_t SYS_CTRL_REGISTERS_T::sleep_enable

◆ sram_lowpower_0

__IO uint32_t SYS_CTRL_REGISTERS_T::sram_lowpower_0

◆ sram_lowpower_1

__IO uint32_t SYS_CTRL_REGISTERS_T::sram_lowpower_1

◆ sram_lowpower_2

__IO uint32_t SYS_CTRL_REGISTERS_T::sram_lowpower_2

◆ sram_lowpower_3

__IO uint32_t SYS_CTRL_REGISTERS_T::sram_lowpower_3

◆ system_clock_control

__IO uint32_t SYS_CTRL_REGISTERS_T::system_clock_control

◆ system_clock_control_0

__IO uint32_t SYS_CTRL_REGISTERS_T::system_clock_control_0

◆ system_clock_control_1

__IO uint32_t SYS_CTRL_REGISTERS_T::system_clock_control_1

◆ system_clock_control_2

__IO uint32_t SYS_CTRL_REGISTERS_T::system_clock_control_2

◆ system_power_state

__IO uint32_t SYS_CTRL_REGISTERS_T::system_power_state

◆ system_test

__IO uint32_t SYS_CTRL_REGISTERS_T::system_test
The documentation for this struct was generated from the following files: