|
Trident IoT SDK
|
|
| |
|
Trident IoT SDK
|
|
|
| |
Collaboration diagram for UART CZ20:Data Structures | |
| struct | tr_hal_uart_settings_t |
Typedefs | |
| typedef void(* | tr_hal_uart_receive_callback_t) (uint8_t received_byte) |
| typedef void(* | tr_hal_uart_event_callback_t) (uint32_t event_bitmask) |
Enumerations | |
| enum | tr_hal_uart_id_t { UART_0_ID = 0 , UART_1_ID = 1 , UART_2_ID = 2 } |
| this type is used to specify a UART ID. On the T32CZ20 there are 3 UARTs available. More... | |
| enum | tr_hal_fifo_trigger_t { FCR_TRIGGER_1_BYTE = 0x00 , FCR_TRIGGER_4_BYTES = 0x40 , FCR_TRIGGER_8_BYTES = 0x80 , FCR_TRIGGER_14_BYTES = 0xC0 , FCR_NO_TRIGGER = 0xFF } |
| values we can trigger on for receive FIFO More... | |
| enum | tr_hal_data_bits_t { LCR_DATA_BITS_5_VALUE = 0x00 , LCR_DATA_BITS_6_VALUE = 0x01 , LCR_DATA_BITS_7_VALUE = 0x02 , LCR_DATA_BITS_8_VALUE = 0x03 , LCR_DATA_BITS_INVALID_VALUE = 0xFF } |
| enum | tr_hal_stop_bits_t { LCR_STOP_BITS_ONE_VALUE = 0x00 , LCR_STOP_BITS_TWO_VALUE = 0x04 , LCR_STOP_BITS_INVALID_VALUE = 0xFF } |
| enum | tr_hal_parity_t { LCR_PARITY_NONE_VALUE = 0x00 , LCR_PARITY_ODD_VALUE = 0x08 , LCR_PARITY_EVEN_VALUE = 0x16 , LCR_PARITY_INVALID_VALUE = 0xFF } |
| enum | tr_hal_hw_fc_t { MCR_NO_FLOW_CONTROL_VALUE = 0x00 , MCR_SET_RTS_READY = 0x02 , MCR_SET_CTS_ENABLED = 0x20 } |
| for setting up hardware flow control More... | |
| enum | tr_hal_baud_rate_t { TR_HAL_UART_BAUD_RATE_2400 = 0 , TR_HAL_UART_BAUD_RATE_4800 = 1 , TR_HAL_UART_BAUD_RATE_9600 = 2 , TR_HAL_UART_BAUD_RATE_14400 = 3 , TR_HAL_UART_BAUD_RATE_19200 = 4 , TR_HAL_UART_BAUD_RATE_28800 = 5 , TR_HAL_UART_BAUD_RATE_38400 = 6 , TR_HAL_UART_BAUD_RATE_57600 = 7 , TR_HAL_UART_BAUD_RATE_76800 = 8 , TR_HAL_UART_BAUD_RATE_115200 = 9 , TR_HAL_UART_BAUD_RATE_230400 = 10 , TR_HAL_UART_BAUD_RATE_500000 = 11 , TR_HAL_UART_BAUD_RATE_1000000 = 12 , TR_HAL_UART_BAUD_RATE_2000000 = 13 , TR_HAL_UART_BAUD_RATE_LPM_2400 = 0 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_4800 = 1 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_9600 = 2 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_14400 = 3 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_19200 = 4 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_28800 = 5 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_38400 = 6 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_57600 = 7 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_76800 = 8 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_115200 = 9 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_230400 = 10 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_500000 = 11 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_1000000 = 12 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LPM_2000000 = 13 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LOW_SPEED_2400 = 0 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LOW_SPEED_4800 = 1 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LOW_SPEED_9600 = 2 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LOW_SPEED_14400 = 3 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LOW_SPEED_19200 = 4 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LOW_SPEED_28800 = 5 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LOW_SPEED_38400 = 6 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LOW_SPEED_57600 = 7 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LOW_SPEED_76800 = 8 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES , TR_HAL_UART_BAUD_RATE_LOW_SPEED_115200 = 9 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES , TR_HAL_UART_BAUD_RATE_SLOW_CLOCK_2400 = 0 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES + TR_HAL_NUM_LOW_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_SLOW_CLOCK_4800 = 1 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES + TR_HAL_NUM_LOW_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_SLOW_CLOCK_9600 = 2 + TR_HAL_NUM_FULL_SPEED_BAUD_RATES + TR_HAL_NUM_LPM_BAUD_RATES + TR_HAL_NUM_LOW_SPEED_BAUD_RATES , TR_HAL_UART_BAUD_RATE_ERROR = TR_HAL_NUM_BAUD_RATES } |
Functions | |
| UART_REGISTERS_T * | tr_hal_uart_get_uart_register_address (tr_hal_uart_id_t uart_id) |
| #define CHIP_MEMORY_MAP_UART0_BASE (0x40012000UL) |
section 2.2 of the data sheet explains the Memory map this gives the base address for how to write the UART registers the UART registers are how the software interacts with the UART peripheral. We create a struct below that addresses the individual registers. This makes it so we can use this base address and a struct field to read or write a chip register
| #define CHIP_MEMORY_MAP_UART1_BASE (0x40013000UL) |
| #define CHIP_MEMORY_MAP_UART2_BASE (0x40025000UL) |
| #define DEFAULT_UART0_CONFIG |
| #define DEFAULT_UART1_CONFIG |
| #define DEFAULT_UART2_CONFIG |
| #define DMA_RX_BUFF_MINIMUM_SIZE 16 |
If using a DMA buffer we enforce a minimum size. This is a software setting, and current set to equal the FIFO RX size
| #define LOW_BYTES_BUFFER_THRESHHOLD 16 |
this sets a threshhold for the number of bytes left in the DMA buffer before we should notify the user via an event. This is a software setting, and it can be adjusted/changed
| #define MAX_RAW_TX_DATA_BUFFER_SIZE 256 |
This defines the maximum size buffer the raw tx API can take in to transmit. this is a software setting, and it can be adjusted. if adjusting, note that this uses 3x the RAM since we have 3 UARTs.
| #define TR_HAL_NUM_BAUD_RATES |
| #define TR_HAL_NUM_FULL_SPEED_BAUD_RATES 14 |
done with doxygen ignoring the code
baud rates - see section 18.3.3 the baud rate is determines by taking the 32 MHz clock and dividing by 8 and also by a configured number. The configured number is a whole number divisor and a fractional divisor the fractional divisor is a number from 1-8 divided by 8.
FOR INSTANCE: for a target of 115200 baud rate
32,000,000 / 8 = 4,000,000 / 115200 = 34.722
divisor would be 34
fractional divisor would be 6/8th which is closest 8th to 0.722
so set divisor_latch_register = 34
and set fractional_divisor_latch = FRAC_DIVISOR_6
we have an enum so the user can specify what baud rate is desired that enum is used to lookup the divisor and fractional divisor to set the 2 registers
DO NOT CHANGE THESE NUMBERS AS THEY ARE USED AS INDICES INTO THE LOOKUP TABLE FOR THE DIVISOR AND FRAC DIVISOR
| #define TR_HAL_NUM_LOW_SPEED_BAUD_RATES 10 |
| #define TR_HAL_NUM_LPM_BAUD_RATES 14 |
| #define TR_HAL_NUM_SLOW_CLOCK_BAUD_RATES 3 |
| #define TR_HAL_PIN_NOT_SET 0xFF |
use for an unset pin
| #define TR_HAL_UART_EVENT_DMA_RX_BUFFER_LOW 0x00000002 |
| #define TR_HAL_UART_EVENT_DMA_RX_READY 0x00000008 |
| #define TR_HAL_UART_EVENT_DMA_RX_TO_USER_FX 0x00000004 |
| #define TR_HAL_UART_EVENT_DMA_TX_COMPLETE 0x00000001 |
these are the EVENTS that can be received into the UART event handler functions. These are BITMASKs since we can have more than 1 in an event these are what the APP needs to handle in its event_handler_fx
| #define TR_HAL_UART_EVENT_HW_FLOW_CONTROL 0x00008000 |
| #define TR_HAL_UART_EVENT_RX_ENDED_NO_DATA 0x00000200 |
| #define TR_HAL_UART_EVENT_RX_ENDED_TO_USER_FX 0x00000100 |
| #define TR_HAL_UART_EVENT_RX_ERR_BREAK 0x00004000 |
| #define TR_HAL_UART_EVENT_RX_ERR_FRAMING 0x00002000 |
| #define TR_HAL_UART_EVENT_RX_ERR_OVERRUN 0x00000800 |
| #define TR_HAL_UART_EVENT_RX_ERR_PARITY 0x00001000 |
| #define TR_HAL_UART_EVENT_RX_MAYBE_READY 0x00000400 |
| #define TR_HAL_UART_EVENT_RX_READY 0x00000080 |
| #define TR_HAL_UART_EVENT_RX_TO_USER_FX 0x00000040 |
| #define TR_HAL_UART_EVENT_TX_COMPLETE 0x00000010 |
| #define TR_HAL_UART_EVENT_TX_STILL_GOING 0x00000020 |
| #define TR_HAL_UART_EVENT_UNEXPECTED 0x00010000 |
| #define TR_NUMBER_OF_UARTS 3 |
the T32CZ20 has 3 UARTs available for configuration. this is a chip constraint - can't change it.
| #define TX_FIFO_SIZE 32 |
This is the size of the RX and TX FIFO. This is a chip constraint - can't change it
| #define UART0_RX_PIN_DEFAULT 16 |
UART0 RX default.
| #define UART0_TX_PIN_DEFAULT 17 |
UART0 TX default.
| #define UART1_RX_PIN_DEFAULT 7 |
UART1 RX default.
| #define UART1_TX_PIN_DEFAULT 6 |
UART1 TX default.
| #define UART2_RX_PIN_DEFAULT 9 |
UART2 RX default.
| #define UART2_TX_PIN_DEFAULT 8 |
UART2 TX default.
| typedef void(* tr_hal_uart_event_callback_t) (uint32_t event_bitmask) |
| typedef void(* tr_hal_uart_receive_callback_t) (uint8_t received_byte) |
| enum tr_hal_baud_rate_t |
| enum tr_hal_data_bits_t |
| enum tr_hal_hw_fc_t |
| enum tr_hal_parity_t |
| enum tr_hal_stop_bits_t |
| enum tr_hal_uart_id_t |
| UART_REGISTERS_T * tr_hal_uart_get_uart_register_address | ( | tr_hal_uart_id_t | uart_id | ) |
the UART can be set to various clock modes The clock mode is chosen to save power or to use a clock that is still running when the chip is sleeping.
the clock to use is set in the SYS_CTRL_CHIP_REGISTERS->system_clock_control_1 register. in the fields: uartO_clk_sel, uart1_clk_sel, uart2_clk_sel
There are 3 options:
the UART clocks are the same as the ones defines in the POWER module as tr_hal_clock_t
if the app wants to directly interface with the chip registers, this is a convenience function for getting the address/struct of a particular UART so the chip registers can be accessed.
EXAMPLE: check LSR and if ready, read a byte from RBR
UART_REGISTERS_T* uart_register_address = tr_hal_uart_get_uart_register_address(2);
if ((uart_register_address->line_status_register) & LSR_DATA_READY)
{
uint8_t rx_data = uart_register_address->receive_buffer_register;
}
1.10.0