Trident IoT SDK
 
Loading...
Searching...
No Matches
Data Fields
SPI_REGISTERS_T Struct Reference
Trident HAL » T32CM11 specific » SPI CM11 | Trident HAL » T32CZ20 specific » SPI CZ20

the struct we use so we can address registers using field names More...

#include <T32CM11_spi.h>

Data Fields

__IO uint32_t spi_tx_data
 
__I uint32_t spi_rx_data
 
__I uint32_t reserved1
 
__IO uint32_t spi_control
 
__IO uint32_t spi_aux_control
 
__I uint32_t spi_status
 
__IO uint32_t peripheral_select
 
__IO uint32_t peripheral_select_polarity
 
__IO uint32_t interrupt_enable
 
__I uint32_t interrupt_status
 
__IO int32_t interrupt_clear
 
__I uint32_t tx_fifo_current_level
 
__I uint32_t rx_fifo_current_level
 
__I uint32_t reserved2
 
__IO uint32_t controller_delay_setting
 
__IO uint32_t spi_enable_disable
 
__IO uint32_t reserved3 [4]
 
__IO uint32_t controller_clock_divider
 
__IO uint32_t reserved4 [3]
 
__IO uint32_t DMA_rx_buffer_addr
 
__IO uint32_t DMA_rx_buffer_len
 
__IO uint32_t DMA_tx_buffer_addr
 
__IO uint32_t DMA_tx_buffer_len
 
__I uint32_t DMA_rx_xfer_len_remaining
 
__I uint32_t DMA_tx_xfer_len_remaining
 
__IO uint32_t DMA_interrupt_enable
 
__IO uint32_t DMA_interrupt_status
 
__IO uint32_t DMA_rx_enable
 
__IO uint32_t DMA_tx_enable
 
__IO uint32_t epd_function
 
__IO uint32_t interrupt_clear
 
__I uint32_t reserved_1
 

Detailed Description

the struct we use so we can address registers using field names

Field Documentation

◆ controller_clock_divider

__IO uint32_t SPI_REGISTERS_T::controller_clock_divider

◆ controller_delay_setting

__IO uint32_t SPI_REGISTERS_T::controller_delay_setting

◆ DMA_interrupt_enable

__IO uint32_t SPI_REGISTERS_T::DMA_interrupt_enable

◆ DMA_interrupt_status

__IO uint32_t SPI_REGISTERS_T::DMA_interrupt_status

◆ DMA_rx_buffer_addr

__IO uint32_t SPI_REGISTERS_T::DMA_rx_buffer_addr

◆ DMA_rx_buffer_len

__IO uint32_t SPI_REGISTERS_T::DMA_rx_buffer_len

◆ DMA_rx_enable

__IO uint32_t SPI_REGISTERS_T::DMA_rx_enable

◆ DMA_rx_xfer_len_remaining

__I uint32_t SPI_REGISTERS_T::DMA_rx_xfer_len_remaining

◆ DMA_tx_buffer_addr

__IO uint32_t SPI_REGISTERS_T::DMA_tx_buffer_addr

◆ DMA_tx_buffer_len

__IO uint32_t SPI_REGISTERS_T::DMA_tx_buffer_len

◆ DMA_tx_enable

__IO uint32_t SPI_REGISTERS_T::DMA_tx_enable

◆ DMA_tx_xfer_len_remaining

__I uint32_t SPI_REGISTERS_T::DMA_tx_xfer_len_remaining

◆ epd_function

__IO uint32_t SPI_REGISTERS_T::epd_function

◆ interrupt_clear [1/2]

__IO int32_t SPI_REGISTERS_T::interrupt_clear

◆ interrupt_clear [2/2]

__IO uint32_t SPI_REGISTERS_T::interrupt_clear

◆ interrupt_enable

__IO uint32_t SPI_REGISTERS_T::interrupt_enable

◆ interrupt_status

__I uint32_t SPI_REGISTERS_T::interrupt_status

◆ peripheral_select

__IO uint32_t SPI_REGISTERS_T::peripheral_select

◆ peripheral_select_polarity

__IO uint32_t SPI_REGISTERS_T::peripheral_select_polarity

◆ reserved1

__I uint32_t SPI_REGISTERS_T::reserved1

◆ reserved2

__I uint32_t SPI_REGISTERS_T::reserved2

◆ reserved3

__IO uint32_t SPI_REGISTERS_T::reserved3[4]

◆ reserved4

__IO uint32_t SPI_REGISTERS_T::reserved4[3]

◆ reserved_1

__I uint32_t SPI_REGISTERS_T::reserved_1

◆ rx_fifo_current_level

__I uint32_t SPI_REGISTERS_T::rx_fifo_current_level

◆ spi_aux_control

__IO uint32_t SPI_REGISTERS_T::spi_aux_control

◆ spi_control

__IO uint32_t SPI_REGISTERS_T::spi_control

◆ spi_enable_disable

__IO uint32_t SPI_REGISTERS_T::spi_enable_disable

◆ spi_rx_data

__I uint32_t SPI_REGISTERS_T::spi_rx_data

◆ spi_status

__I uint32_t SPI_REGISTERS_T::spi_status

◆ spi_tx_data

__IO uint32_t SPI_REGISTERS_T::spi_tx_data

◆ tx_fifo_current_level

__I uint32_t SPI_REGISTERS_T::tx_fifo_current_level
The documentation for this struct was generated from the following files: