The T32CZ20B Z-Wave chip contains both Flash and SRAM with the following default layout
Address | Size | Description |
---|---|---|
0x100FF000 | 4KB | Chip production data |
0x100FE800 | 2KB | Application Tokens |
0x100FE000 | 2KB | Z-Wave protocol Tokens |
0x10099000 | 404KB | OTA Image storage |
0x10085000 | 80KB | NVM Storage |
0x10008000 | 500KB | Z-Wave Stack and Application |
0x10000000 | 32KB | Boot Loader |
Address | Size | Description |
---|---|---|
0x10028000 | 32KB | Bank 3 |
0x10020000 | 32KB | Bank 2 |
0x10010000 | 64KB | Bank 1 |
0x30000000 | 64KB | Bank 0 |
Memory access to different banks can occure concurrently and can boost the performance of the memory access from the CPU.