T32CM11_sysctrl.h

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#ifndef T32CM11_SYSCTRL_H_
#define T32CM11_SYSCTRL_H_
 
#include "tr_hal_platform.h"


#define TR_HAL_NUM_PULL_REGISTERS 4
#define TR_HAL_PINS_PER_PULL_REG 8
 
#define TR_HAL_NUM_MODE_REGISTERS 4
#define TR_HAL_PINS_PER_MODE_REG 8
 
#define TR_HAL_NUM_DRIVE_REGISTERS 2
#define TR_HAL_PINS_PER_DRIVE_REG 16
 

typedef struct
{
    __IO uint32_t sleep_enable;          // 0x00
    __IO uint32_t system_clock_control;  // 0x04
    __IO uint32_t reserved[2];           // 0x08, 0x0C
 
    // default is 0 = GPIO
    __IO uint32_t gpio_pin_map[TR_HAL_NUM_MODE_REGISTERS];   // 0x10, 0x14, 0x18, 0x1C
 
    // default is 0b110 = 6 = 100K pull up
    __IO uint32_t gpio_pull_ctrl[TR_HAL_NUM_PULL_REGISTERS]; // 0x20, 0x24, 0x28, 0x2C
 
    // default is 0b11 = 3 = 20 mA (max)
    __IO uint32_t gpio_drv_ctrl[TR_HAL_NUM_DRIVE_REGISTERS]; // 0x30, 0x34
 
    // default is 0 = disabled
    __IO uint32_t open_drain_enable;     // 0x38
 
    // note this only works for pins 24-31, of which 24-27 are not available
    // lowest 8 bits are used to enable these 8 pins
    // bit 0 = pin 24... bit 7 = pin 31
    __IO uint32_t analog_IO_enable;     // 0x3C
 
    // random number generator registers (see section 20)
    __IO uint32_t random_number_trigger; // 0x40
    __IO uint32_t random_number_select;  // 0x44
    __IO uint32_t random_number_status;  // 0x48
    __IO uint32_t random_number_value;   // 0x4C
 
    // reserved
    __IO uint32_t reserved2[4];          // 0x50, 0x54, 0x58, 0x5C
    __IO uint32_t scratchpad[8];         // 0x60, 0x64, 0x68, 0x6C, 0x70, 0x74, 0x78, 0x7C
 
    // wake from sleep on low-to-high transition of GPIO
    __IO uint32_t enable_wake_on_high;   // 0x80
 
    // wake from sleep on high-to-low transition of GPIO
    __IO uint32_t enable_wake_on_low;    // 0x84
 
    // reserved
    __IO uint32_t reserved3[2];          // 0x88, 0x8C
 
    // chip info
    // bit 4 to bit 7 (0x000000F0) is the chip revision
    // bit 8 to bit 15 (0x0000FF00) is the chip ID
    __IO uint32_t chip_info;             // 0x90
 
} SYS_CTRL_REGISTERS_T;
 
// *****************************************************************
// this orients the SYSCTRL_REGISTERS struct with the correct addresses
// so referencing a field will now read/write the correct SYSCTRL register
// chip address
#define SYS_CTRL_CHIP_REGISTERS  ((SYS_CTRL_REGISTERS_T *) CHIP_MEMORY_MAP_SYS_CTRL_BASE)
 
// these are for setting the system_clock_control register
#define SCC_UART0_CLOCK_BIT      16
#define SCC_UART1_CLOCK_BIT      17
#define SCC_UART2_CLOCK_BIT      18
 
#define TR_HAL_ENABLE_LITE_SLEEP 1
#define TR_HAL_ENABLE_DEEP_SLEEP 2

 
#endif // T32CM11_SYSCTRL_H_