T32CZ20_sysctrl.h

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#ifndef T32CZ20_SYSCTRL_H_
#define T32CZ20_SYSCTRL_H_
 
#include "tr_hal_platform.h"
 

 

#define TR_HAL_NUM_PULL_REGISTERS 4
#define TR_HAL_PINS_PER_PULL_REG 8
 
#define TR_HAL_NUM_DRIVE_REGISTERS 2
#define TR_HAL_PINS_PER_DRIVE_REG 16
 

typedef struct
{
    // bit 4 to bit 7 (0x000000F0) is the chip revision
    // bit 8 to bit 15 (0x0000FF00) is the chip ID
    __IO uint32_t chip_info;              // 0x00
 
    // select which real clock to use for virtual clocks: hclk, per_clk, slow_clk
    // and configure baseband frequency
    __IO uint32_t system_clock_control_0; // 0x04
 
    // select clk for UARTs, external slow clk, PWM, timers 0,1,2
    __IO uint32_t system_clock_control_1; // 0x08
 
    __IO uint32_t system_power_state;     // 0x0C
 
    // default is 0 = GPIO
    __IO uint32_t reserved_old_map[4];    // 0x10, 0x14, 0x18, 0x1C
    //__IO uint32_t gpio_pin_map[4];      // 0x10, 0x14, 0x18, 0x1C
 
    // default is 0b110 = 6 = 100K pull up
    __IO uint32_t gpio_pull_ctrl[TR_HAL_NUM_PULL_REGISTERS]; // 0x20, 0x24, 0x28, 0x2C
 
    // default is 0b11 = 3 = 20 mA (max)
    __IO uint32_t gpio_drv_ctrl[TR_HAL_NUM_DRIVE_REGISTERS]; // 0x30, 0x34
 
    // default is 0 = disabled
    __IO uint32_t open_drain_enable;      // 0x38
 
    __IO uint32_t enable_schmitt;         // 0x3C
    __IO uint32_t enable_filter;          // 0x40
    __IO uint32_t aio_control;            // 0x44
    __IO uint32_t cache_control;          // 0x48
    __IO uint32_t pwm_select;             // 0x4C
 
    // these are for telling the system how to power the RAM when in a power down
    // mode. The RAM can be retained or not retained
    __IO uint32_t sram_lowpower_0;        // 0x50
    __IO uint32_t sram_lowpower_1;        // 0x54
    __IO uint32_t sram_lowpower_2;        // 0x58
    __IO uint32_t sram_lowpower_3;        // 0x5C
 
    __IO uint32_t system_clock_control_2; // 0x60
    __IO uint32_t system_test;            // 0x64
    __IO uint32_t reserved[6];            // 0x68 - 0x7C
 
    // for setting GPIO pins as output functions
    __IO uint32_t gpio_output_mux[8];     // 0x80 - 0x9C
 
    // for setting GPIO pins as input functions
    // note that the reg at 0xAC == IMUX3 == 4th register == gpio_input_mux[3] is NOT CURRENTLY USED
    __IO uint32_t gpio_input_mux[8];      // 0xA0 - 0xBC
 
} SYS_CTRL_REGISTERS_T;
 
// *****************************************************************
// this is for the SYSTEM CLOCK CONTROL 0 register (0x04)
 
// bits 0,1 = HCLK select
// hclk: host clock (host, AHB, memory, DMA, flash, I2S, crypto)
#define SYS_CTRL_HCLK_SELECT_XTAL_CLK        0x00
#define SYS_CTRL_HCLK_SELECT_PLL_CLK         0x01
#define SYS_CTRL_HCLK_SELECT_XTAL_CLK_DIV2   0x02
#define SYS_CTRL_HCLK_SELECT_RCO_1M          0x03
#define SYS_CTRL_HCLK_SELECT_MASK            0x03
 
// bits 2,3 = PER CLK select
// per clk: wdog, I2C, SPI
#define SYS_CTRL_PER_CLK_SELECT_XTAL_CLK      0x00
#define SYS_CTRL_PER_CLK_SELECT_XTAL_CLK_DIV2 0x04
#define SYS_CTRL_PER_CLK_SELECT_RCO_1M        0x08
#define SYS_CTRL_PER_CLK_SELECT_MASK          0x0C
 
// bits 4,5 reserved
 
// bits 6,7 = SLOW CLK select
// slow_clk: RTC, timers 3,4
#define SYS_CTRL_SLOW_CLK_SELECT_RCO_32K  0x00
#define SYS_CTRL_SLOW_CLK_SELECT_XO_32K   0x40
#define SYS_CTRL_SLOW_CLK_SELECT_EXTERNAL 0xC0
#define SYS_CTRL_SLOW_CLK_SELECT_MASK     0xC0
 
// bits 8,9,10 = baseband frequency
#define SYS_CTRL_BASEBAND_FREQ_48_MHZ 0x00
#define SYS_CTRL_BASEBAND_FREQ_64_MHZ 0x100
#define SYS_CTRL_BASEBAND_FREQ_36_MHZ 0x600
#define SYS_CTRL_BASEBAND_FREQ_40_MHZ 0x700
 
// bits 11-14 reserved
 
// bit 15 - baseband PLL enable
#define SYS_CTRL_BASEBAND_PLL_ENABLE  0x8000
#define SYS_CTRL_BASEBAND_PLL_DISABLE 0x0000
 
 
// *****************************************************************
// this is for the SYSTEM CLOCK CONTROL 1 register (0x08)
 
// bits 0,1 UART0 clock select
// bits 2,3 UART1 clock select
// bits 4,5 UART2 clock select
 
// these are the values, and will need to be shifted based on the UART
// this is for bits 0 thru 5
#define SYS_CTRL_UART_CLOCK_SELECT_PER_CLOCK 0x00
#define SYS_CTRL_UART_CLOCK_SELECT_RCO_1M    0x02
#define SYS_CTRL_UART_CLOCK_SELECT_RCO_32K   0x03
 
#define SYS_CTRL_UART0_CLOCK_SELECT_BIT_SHIFT 0
#define SYS_CTRL_UART1_CLOCK_SELECT_BIT_SHIFT 2
#define SYS_CTRL_UART2_CLOCK_SELECT_BIT_SHIFT 4
 
// bits 6,7 reserved
 
// bits 8 to 13 are for setting the slow clock to an external clock
 
// bit 13 set = enable slow clock to use external source
#define SYS_CTRL_SLOW_CLK_ENABLE_EXTERNAL 0x2000
 
// the external clock source is a GPIO number, in bits 8 to 12
// so shift the GPIO number by this amount of bits
#define SYS_CTRL_SLOW_CLK_EXTERNAL_SRC_SHIFT 8
 
// bits 16,17 = PWM0 clock select
// bits 18,19 = PWM1 clock select
// bits 20,21 = PWM2 clock select
// bits 22,23 = PWM3 clock select
// bits 24,25 = PWM4 clock select
 
#define SYS_CTRL_PWM_CLOCK_SELECT_HCLK     0x00
#define SYS_CTRL_PWM_CLOCK_SELECT_PER_CLK  0x01
#define SYS_CTRL_PWM_CLOCK_SELECT_RCO_1M   0x02
#define SYS_CTRL_PWM_CLOCK_SELECT_SLOW_CLK 0x03
 
#define SYS_CTRL_PWM0_CLOCK_SELECT_BIT_SHIFT 16
#define SYS_CTRL_PWM1_CLOCK_SELECT_BIT_SHIFT 18
#define SYS_CTRL_PWM2_CLOCK_SELECT_BIT_SHIFT 20
#define SYS_CTRL_PWM3_CLOCK_SELECT_BIT_SHIFT 22
#define SYS_CTRL_PWM4_CLOCK_SELECT_BIT_SHIFT 24
 
// bits 26,27 = Timer0 clock select
// bits 28,29 = Timer1 clock select
// bits 30,31 = Timer2 clock select
 
#define SYS_CTRL_TIMER_CLOCK_SELECT_PER_CLK  0x00
#define SYS_CTRL_TIMER_CLOCK_SELECT_RCO_1M   0x02
#define SYS_CTRL_TIMER_CLOCK_SELECT_SLOW_CLK 0x03
 
#define SYS_CTRL_TIMER0_CLOCK_SELECT_BIT_SHIFT 26
#define SYS_CTRL_TIMER1_CLOCK_SELECT_BIT_SHIFT 28
#define SYS_CTRL_TIMER2_CLOCK_SELECT_BIT_SHIFT 30
 
 
// *****************************************************************
// this is for the SYSTEM POWER STATE register (0x0C)
#define TR_HAL_POWER_NORMAL     0x00
#define TR_HAL_POWER_LITE_SLEEP 0x01
#define TR_HAL_POWER_DEEP_SLEEP 0x02
#define TR_HAL_POWER_POWERDOWN  0x04
 
 
// *****************************************************************
// this orients the SYSCTRL_REGISTERS struct with the correct addresses
// so referencing a field will now read/write the correct SYSCTRL register
// chip address
#define SYS_CTRL_CHIP_REGISTERS  ((SYS_CTRL_REGISTERS_T *) CHIP_MEMORY_MAP_SYS_CTRL_BASE)
 
// these are for setting the system_clock_control register
#define     SCC_UART0_CLOCK_BIT                 16
#define     SCC_UART1_CLOCK_BIT                 17
#define     SCC_UART2_CLOCK_BIT                 18

 
#endif // T32CZ20_SYSCTRL_H_