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Data Structures | Macros | Typedefs | Enumerations | Functions
T32CM11_spi.h File Reference

This is the chip specific include file for T32CM11 SPI Driver note that there is a common include file for this HAL module that contains the APIs (such as the init function) that should be used by the application. More...

#include "tr_hal_platform.h"
+ Include dependency graph for T32CM11_spi.h:
+ This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct  SPI_REGISTERS_T
 the struct we use so we can address registers using field names More...
 
struct  tr_hal_spi_settings_t
 

Macros

#define TR_HAL_NUM_SPI   2
 
#define TR_HAL_SPI_TX_FIFO_SIZE   32
 
#define TR_HAL_SPI_RX_FIFO_SIZE   32
 
#define SPI0_CLK_BIT   20
 
#define SPI1_CLK_BIT   21
 
#define SPI0_CLK_ENABLE_VALUE   0x100000
 
#define SPI1_CLK_ENABLE_VALUE   0x200000
 
#define SPI_INVALID_PIN   0xFF
 
#define SPI0_CLK_PIN_OPTION1   6
 
#define SPI0_CLK_PIN_OPTION2   28
 
#define SPI0_IO0_PIN_OPTION1   8
 
#define SPI0_IO0_PIN_OPTION2   30
 
#define SPI0_IO1_PIN_OPTION1   9
 
#define SPI0_IO1_PIN_OPTION2   31
 
#define SPI0_IO2_PIN_OPTION1   4
 
#define SPI0_IO2_PIN_OPTION2   14
 
#define SPI0_IO3_PIN_OPTION1   5
 
#define SPI0_IO3_PIN_OPTION2   15
 
#define SPI0_MAX_CHIP_SELECT_PINS   4
 
#define SPI0_CS0_PIN_OPTION1   7
 
#define SPI0_CS0_PIN_OPTION2   29
 
#define SPI0_CS1_PIN_OPTION1   1
 
#define SPI0_CS1_PIN_OPTION2   2
 
#define SPI0_CS1_PIN_OPTION3   3
 
#define SPI0_CS1_PIN_OPTION4   4
 
#define SPI0_CS2_PIN_OPTION1   1
 
#define SPI0_CS2_PIN_OPTION2   2
 
#define SPI0_CS2_PIN_OPTION3   3
 
#define SPI0_CS2_PIN_OPTION4   4
 
#define SPI0_CS3_PIN_OPTION1   1
 
#define SPI0_CS3_PIN_OPTION2   2
 
#define SPI0_CS3_PIN_OPTION3   3
 
#define SPI0_CS3_PIN_OPTION4   4
 
#define SPI1_CLK_PIN_OPTION1   28
 
#define SPI1_IO0_PIN_OPTION1   30
 
#define SPI1_IO1_PIN_OPTION1   31
 
#define SPI1_MAX_CHIP_SELECT_PINS   1
 
#define SPI1_CS0_PIN_OPTION1   29
 
#define CHIP_MEMORY_MAP_SPI0_BASE   (0xB0000000UL)
 chip register addresses section 3.1 of the data sheet explains the Memory map. this gives the base address for how to write the chip registers the chip registers are how the software interacts and configures the SPI peripherals. We create a struct below that addresses the individual registers. This makes it so we can use this base address and a struct field to read or write a chip register
 
#define CHIP_MEMORY_MAP_SPI1_BASE   (0x80000000UL)
 
#define SPI0_REGISTERS   ((SPI_REGISTERS_T *) CHIP_MEMORY_MAP_SPI0_BASE)
 
#define SPI1_REGISTERS   ((SPI_REGISTERS_T *) CHIP_MEMORY_MAP_SPI1_BASE)
 
#define SPI_STATUS_TX_IN_PROGRESS   0x01
 
#define SPI_STATUS_TX_FIFO_EMPTY   0x04
 
#define SPI_STATUS_TX_FIFO_WMARK   0x08
 
#define SPI_STATUS_TX_FIFO_FULL   0x10
 
#define SPI_STATUS_RX_FIFO_EMPTY   0x20
 
#define SPI_STATUS_RX_FIFO_WMARK   0x40
 
#define SPI_STATUS_RX_FIFO_FULL   0x80
 
#define SPI_CONTROL_REG_CONTINUOUS_TRANSFER   0x01
 
#define SPI_CONTROL_REG_BYTE_SWAP   0x02
 
#define SPI_CONTROL_REG_MSB_FIRST   0x04
 
#define SPI_CONTROL_REG_CPHA_HIGH   0x08
 
#define SPI_CONTROL_REG_CPHA_LOW   0x00
 
#define SPI_CONTROL_REG_CPOL_HIGH   0x10
 
#define SPI_CONTROL_REG_CPOL_LOW   0x00
 
#define SPI_CONTROL_REG_SET_AS_CONTROLLER   0x20
 
#define SPI_CONTROL_REG_SET_AS_PERIPHERAL   0x00
 
#define SPI_CONTROL_REG_SDATA_FOR_CROSSED   0x40
 
#define SPI_CONTROL_REG_ENABLE_CONTROLLER_DELAY   0x800
 
#define SPI_CONTROL_REG_RX_WMARK_MASK   0x3000
 
#define SPI_CONTROL_REG_TX_WMARK_MASK   0xC000
 
#define SPI_AUX_CTRL_REG_MODE_MASK   0x03
 
#define SPI_AUX_CTRL_REG_PREVENT_TX_BIT   0x04
 
#define SPI_AUX_CTRL_REG_PREVENT_RX_BIT   0x08
 
#define SPI_AUX_CTRL_REG_BITSIZE_MASK   0x70
 
#define SPI_AUX_CTRL_REG_TRANSFER_EXTEND   0x80
 
#define SPI_INTERRUPT_TX_EMPTY   0x01
 
#define SPI_INTERRUPT_TX_WATERMARK   0x02
 
#define SPI_INTERRUPT_RX_WATERMARK   0x04
 
#define SPI_INTERRUPT_RX_FULL   0x08
 
#define SPI_INTERRUPT_TRANSFER_DONE   0x10
 
#define SPI_INTERRUPT_RX_NOT_EMPTY   0x20
 
#define SPI_INTERRUPT_ALL   0x3F
 
#define SPI_INTERRUPT_NONE   0x00
 
#define SPI_PERIPH_SELECT_NONE   0x00
 
#define SPI_PERIPH_SELECT_0   0x01
 
#define SPI_PERIPH_SELECT_1   0x02
 
#define SPI_PERIPH_SELECT_2   0x04
 
#define SPI_PERIPH_SELECT_3   0x08
 
#define SPI_PERIPH_SELECT_CONTROLLER_ACTIVE_LOW   0x00
 
#define SPI_PERIPH_SELECT_CONTROLLER_ACTIVE_HIGH   0x0F
 
#define SPI_ENABLE   0x01
 
#define SPI_DISABLE   0x00
 
#define SPI_DMA_INTERRUPTS_DISABLE   0x00
 
#define SPI_DMA_RX_INTERRUPT_ENABLE   0x01
 
#define SPI_DMA_TX_INTERRUPT_ENABLE   0x02
 
#define SPI_DMA_RX_INTERRUPT_ACTIVE   0x01
 
#define SPI_DMA_TX_INTERRUPT_ACTIVE   0x02
 
#define SPI_DMA_ENABLE   0x01
 
#define SPI_DMA_DISABLE   0x00
 
#define SPI_DMA_RX_BUFF_MINIMUM_SIZE   16
 
#define TR_HAL_SPI_EVENT_TX_EMPTY   0x00000001
 
#define TR_HAL_SPI_EVENT_TX_WMARK   0x00000002
 
#define TR_HAL_SPI_EVENT_RX_WMARK   0x00000004
 
#define TR_HAL_SPI_EVENT_RX_FULL   0x00000008
 
#define TR_HAL_SPI_EVENT_RX_HAS_MORE_DATA   0x00000010
 
#define TR_HAL_SPI_EVENT_TRANSFER_DONE   0x00000020
 
#define TR_HAL_SPI_EVENT_RX_TO_USER_FX   0x00000040
 
#define TR_HAL_SPI_EVENT_RX_READY   0x00000080
 
#define TR_HAL_SPI_EVENT_DMA_RX_TO_USER_FX   0x00000100
 
#define TR_HAL_SPI_EVENT_DMA_RX_READY   0x00000200
 
#define TR_HAL_SPI_EVENT_DMA_TX_COMPLETE   0x00000400
 
#define SPI_CONFIG_CONTROLLER_NORMAL_MODE
 

Typedefs

typedef void(* tr_hal_spi_receive_callback_t) (uint8_t num_received_bytes, uint8_t *byte_buffer)
 
typedef void(* tr_hal_spi_event_callback_t) (tr_hal_spi_id_t spi_id, uint32_t event_bitmask)
 

Enumerations

enum  tr_hal_spi_id_t {
  SPI_0_ID = 0 ,
  SPI_1_ID = 1
}
 
enum  tr_hal_spi_mode_t {
  TR_HAL_SPI_MODE_NORMAL = 0 ,
  TR_HAL_SPI_MODE_DUAL = 2 ,
  TR_HAL_SPI_MODE_QUAD = 3
}
 Normal SPI vs Dual SPI vs Quad SPI modes. More...
 
enum  tr_hal_spi_bit_size_t {
  TR_HAL_SPI_BIT_SIZE_8 = 0x10 ,
  TR_HAL_SPI_BIT_SIZE_32 = 0x70
}
 
enum  tr_hal_spi_rx_watermark_level_t {
  TR_HAL_SPI_RX_WATERMARK_LEVEL_8 = 0x1000 ,
  TR_HAL_SPI_RX_WATERMARK_LEVEL_16 = 0x2000 ,
  TR_HAL_SPI_RX_WATERMARK_LEVEL_24 = 0x3000
}
 
enum  tr_hal_spi_tx_watermark_level_t {
  TR_HAL_SPI_TX_WATERMARK_LEVEL_8 = 0x4000 ,
  TR_HAL_SPI_TX_WATERMARK_LEVEL_16 = 0x8000 ,
  TR_HAL_SPI_TX_WATERMARK_LEVEL_24 = 0xC000
}
 
enum  tr_hal_spi_clock_rate_t {
  SPI_CTRL_CLOCK_32_MHZ = 0x000 ,
  SPI_CTRL_CLOCK_16_MHZ = 0x100 ,
  SPI_CTRL_CLOCK_8_MHZ = 0x101 ,
  SPI_CTRL_CLOCK_4_MHZ = 0x103 ,
  SPI_CTRL_CLOCK_2_MHZ = 0x107 ,
  SPI_CTRL_CLOCK_1_MHZ = 0x10F ,
  SPI_CTRL_CLOCK_500_KHZ = 0x11F ,
  SPI_CTRL_CLOCK_250_KHZ = 0x13F ,
  SPI_CTRL_CLOCK_125_KHZ = 0x17F
}
 

Functions

SPI_REGISTERS_T * tr_hal_spi_get_register_address (tr_hal_spi_id_t spi_id)
 
tr_hal_status_t tr_hal_spi_power_off (tr_hal_spi_id_t spi_id)
 
tr_hal_status_t tr_hal_spi_power_on (tr_hal_spi_id_t spi_id)
 
tr_hal_status_t tr_hal_spi_set_standard_pins (tr_hal_spi_id_t spi_id, tr_hal_gpio_pin_t clk_pin, tr_hal_gpio_pin_t chip_select_0_pin, tr_hal_gpio_pin_t sdo_pin, tr_hal_gpio_pin_t sdi_pin)
 
tr_hal_status_t tr_hal_spi_set_addl_cs_pins (tr_hal_spi_id_t spi_id, uint8_t num_chip_select, tr_hal_gpio_pin_t chip_select_1_pin, tr_hal_gpio_pin_t chip_select_2_pin, tr_hal_gpio_pin_t chip_select_3_pin)
 
tr_hal_status_t tr_hal_spi_read_stats (tr_hal_spi_id_t spi_id, uint32_t *transmit_started, uint32_t *transmit_completed, uint32_t *bytes_received)
 
tr_hal_status_t tr_hal_spi_clear_tx_busy (tr_hal_spi_id_t spi_id)
 

Detailed Description

This is the chip specific include file for T32CM11 SPI Driver note that there is a common include file for this HAL module that contains the APIs (such as the init function) that should be used by the application.

this chip supports 2 SPIs. It supports standard SPI, and Dual and Quad SPI. see below for more information on standard SPI vs Dual SPI vs Quad SPI

SPDX-License-Identifier: LicenseRef-TridentMSLA SPDX-FileCopyrightText: 2025 Trident IoT, LLC https://www.tridentiot.com